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RISC processor device and multi-mode data processing method

A data processing and processor technology, applied in the field of computer microprocessors, can solve problems such as reducing processor performance, achieve the effects of increasing computing speed, saving translation time, and improving performance

Active Publication Date: 2011-08-31
LOONGSON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, in the prior art, since the virtual machine needs to execute a large amount of code during operation, the semantics of the same instruction are different when executed on different virtual machines, that is, the same instruction is executed on a RISC processor and an X86 processor. The semantics are different. For example, in addition to the calculation result, the addition instruction x86 also needs to calculate the EFLAG flag bit according to the result. In this way, during the processor translation process, a lot of translation work is required, thereby reducing the processor overall. performance

Method used

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  • RISC processor device and multi-mode data processing method

Examples

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Embodiment 1

[0068] As an implementable mode, the judging module of the RISC processor device of the present invention is a first control register 1, and the first control register 1 includes a control bit flag X86MODE1, and when this bit is 1, it means that at this time The corresponding instruction runs in the X86 virtual machine instruction set mode; when the flag is 0, it means that the corresponding instruction runs in the non-X86 virtual machine instruction set mode at this time.

[0069] In the MIPS64 instruction set of the RISC processor, some Coprocessor0 (CP0) control registers are reserved for user-defined. For example, register No. 22 is reserved for user-defined in the case of all Sel bits.

[0070] Embodiments of the present invention utilize one of these control registers (CP0) as the X86 mode control flag X86MODE1. When it is necessary to distinguish the mode of the instruction, it can be judged by reading the corresponding bit of the control register. When the flag bit is ...

Embodiment 2

[0075] As an implementable mode, in the RISC processor device of the present invention, the judgment module is a prefix instruction module 21 included in the instruction decoder 2, and the prefix instruction module 21 includes a prefix instruction X86MODE2 for Indicates that multiple instructions following the instruction are in the X86 virtual machine instruction set mode.

[0076] For the prefix instruction in the prefix instruction module 21 of the embodiment of the present invention, the format in the MIPS64 instruction set of the RISC processor is as follows figure 2 As shown, it is implemented using the reserved value of the empty slot of SPECIAL2 in the MIPS instruction set.

[0077] The prefix instruction module 21 of the instruction decoder 2 sets a flag when decoding the prefix instruction, and the instruction behind this instruction is translated into the X86 virtual machine instruction set mode, and then the prefix instruction is translated into an empty operation...

Embodiment 3

[0085] As another implementable manner, the judging module is an instruction mode module 23, configured to mark the virtual machine instruction set mode of the instruction in the MIPS instruction of the RISC processor.

[0086] For the X86 virtual machine instruction with high frequency of use, it is necessary to set a sign in the MIPS instruction set of the RISC processor through the instruction mode module 23, indicating that the MIPS instruction is an instruction executed under the X86 virtual machine instruction set mode . In this way, for frequently used X86 virtual machine instructions, the instruction is marked as the X86 virtual machine instruction set mode, and is directly executed by the MIPS instruction set of the RISC processor, so as to reduce the corresponding overhead.

[0087] The instructions affected by the instruction mode module 23 can only affect the decoding and execution of the instruction, and have no effect on other instructions, and other instructions...

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Abstract

The invention discloses a RISC processor device and a multi-mode lower data process method, the processor device comprises a judging mode, an instruction decipherer, and a calculating component, wherein the judging mode is used for distinguishing virtual machine instruction catalogue mode which is instructed, the instruction decipherer is used for deciphering the instruction according to the virtual machine instruction catalogue mode which is distinguished by the judging mode according to the virtual machine instruction catalogue mode which is distinguished, and outputting the instruction to the calculating component during the process of instruction deciphering, the calculating component is used for processing according to the output of the instruction decipherer and outputting the executive result. The invention greatly improves performance of a computer.

Description

technical field [0001] The invention relates to the technical field of computer microprocessors, in particular to a complex instruction set computer (RISC) processor device and its data processing method in various virtual machine operating modes. Background technique [0002] Complex Instruction Set Computing (CISC) and Reduced Instruction Set Computing (RISC) are two architectures of current CPUs. Processors with different architectures can only execute their own instruction sets. For example, Intel machines can only execute 80X86 instruction sets (a CISC instruction set), but cannot execute RISC instruction sets; while RISC architecture calculations cannot execute 80X86 instruction sets . Due to the difference in hardware architecture, the operating system and various application software can only be executed on a computer with a specific architecture. For example, a microprocessor with a RISC architecture cannot fully utilize the existing extensive application software ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F9/455
Inventor 李晓钰苏孟豪
Owner LOONGSON TECH CORP
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