Estimation method for integrate circuit function yield

Abstract

The invention discloses a function pass rate estimating method for an integrated circuit, aiming at solving the problem of low accuracy of the existing estimating method. Adopting different pass rate estimating methods for different types of errors, the invention comprises the steps as follows: each layer of plane layout of the to-be-estimated integrated circuits is numbered according to wire mesh; the error shape feature is extracted in production procedures corresponding to of the plane layout of the to-be-estimated integrated circuits; the error shape feature is divided into three grades of a circular outline, an elliptic outline and a random outline; the key areas of the errors of the circular outline, the elliptic outline and the random outline are calculated on a selected plane layout respectively, summing up to gain the total key area of the three errors on the selected plane layout; the pass rate of corresponding processes and the pass rate of the integrated circuit in the selected plane layout are estimated by utilizing a normal method according to the total sum. The invention characterized by high estimating accuracy is applicable for affirmation about the pass rate loss estimation of chips caused by the errors of random shape during the producing process.

Description

technical field [0001] The present invention relates to the estimation of functional yields caused by random defects in IC (integrated circuit) manufacturing, and more precisely, to methods for determining chip yield losses caused by randomly shaped defects in the manufacturing process, the results of which can be used to predict and improve Yield of integrated circuit chips. Background technique [0002] Yield estimates are an important indicator of profitability for semiconductor fabs. For newly introduced process lines, the yield rate is generally only 20%. In order to ensure the benefit of the manufacturing plant, the reasons for the loss of yield should be quickly analyzed. In the investigation of the cause of yield loss, accurate estimation of yield is the premise. For a mature process line, before chip development and mass production, through accurate estimation of the yield, measures such as changing the layout shape, design rules and process conditions can maximi...

AI Technical Summary

Problems solved by technology

In terms of yield estimation method, the traditional circular defect model method is still used, which results in a larger yield estimation error

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