Method for manufacturing three-dimensional nerve microelectrode

A manufacturing method and micro-electrode technology, applied in the direction of micro-structure technology, micro-structure devices, manufacturing micro-structure devices, etc., can solve the problems of large influence of insulating layer process, easy to generate pinholes, unfavorable long-term implantation, etc., and achieve production cost The effect of reducing and eliminating pinholes and good consistency of electrical characteristics

Active Publication Date: 2008-04-30
上海华实投资有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] Found through literature search to prior art, Peter Norlin et al published on Journal ofmicromechanics and Microengineering (micromechanics and microengineering periodical) (2002, 12 phases, 414-419 pages) ("A 32-site neural recording probe fabricated by DRIE of SOI substrates") (fabrication of 32 recording point electrodes on SOI substrates), this article proposes to use silicon deep etching process to fabricate silicon microelectrodes, the specific method is to use deep reactive ion etching (DRIE) technology to determine the electrode structure, SiO 2 and Si 3 N 4 As an electrical insulating layer, its disadvantage is that the microelectrode is a planar structure, and the insulating layer is greatly affected by the process, which is prone to pinholes, which is not conducive to long-term implantation in the body.

Method used

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  • Method for manufacturing three-dimensional nerve microelectrode
  • Method for manufacturing three-dimensional nerve microelectrode

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Experimental program
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Embodiment 1

[0025] In this embodiment, the cylindrical hole 8 made of SU-8 glue has a height of 100 micrometers and is used for sticking on the surface of the dura mater of the optic nerve or cerebral cortex to stimulate the optic nerve or cerebral cortex to restore nerve function.

[0026] As shown in Figure 1, this embodiment includes the following steps:

[0027] Step 1, clean the silicon wafer 1, use the silicon wafer 1 as the substrate, and use PECVD (plasma chemical vapor deposition) method to grow the bottom SiO on the polished surface of the silicon wafer 1 2 2. Bottom SiO2 2 2 is used to electrically isolate the metal alloy layer from the silicon substrate, as shown in Figure 1(a).

[0028] The silicon wafer 1 is N-type single crystal silicon.

[0029] Step 2, on the bottom SiO 2 Metal titanium and gold are sequentially sputtered on 2 to form a metal alloy layer, and metal interconnection lines 3, pads 5 and contact dots 6 are etched out. Dot 6 is used to electroplate and gro...

Embodiment 2

[0036] In this embodiment, the cylindrical hole 8 made of SU-8 glue has a height of 500 micrometers and is used to penetrate the dura mater and stick on the surface of the pia mater to stimulate the optic nerve or cerebral cortex to restore nerve function.

[0037] As shown in Figure 1, this embodiment includes the following steps:

[0038] Step 1, clean the silicon wafer 1, use the silicon wafer 1 as the substrate, and use PECVD (plasma chemical vapor deposition) method to grow the bottom SiO on the polished surface of the silicon wafer 1 2 2. Bottom SiO2 2 2 is used to electrically isolate the metal alloy layer from the silicon substrate, as shown in Figure 1(a).

[0039] The silicon wafer 1 is P-type single crystal silicon.

[0040] Step 2, on the bottom SiO 2 Metal titanium and gold are sequentially sputtered on 2 to form a metal alloy layer, and metal interconnection lines 3, pads 5 and contact dots 6 are etched out. Dot 6 is used to electroplate and grow cylindrical ...

Embodiment 3

[0047] The height of the cylindrical hole 8 that adopts SU-8 glue to form among the present embodiment is 1 millimeter, is used for penetrating dura mater and pia mater, punctures in optic nerve or cerebral cortex, is used for stimulating optic nerve or cerebral cortex, carries out neural Functional fixes.

[0048] As shown in Figure 1, this embodiment includes the following steps:

[0049] Step 1, clean the silicon wafer 1, use the silicon wafer 1 as the substrate, and use PECVD (plasma chemical vapor deposition) method to grow the bottom SiO on the polished surface of the silicon wafer 1 2 2. Bottom SiO2 2 2 is used to electrically isolate the metal alloy layer from the silicon substrate, as shown in Figure 1(a).

[0050] The silicon wafer 1 is N-type single crystal silicon.

[0051] Step 2, on the bottom SiO 2 Metal titanium and gold are sequentially sputtered on 2 to form a metal alloy layer, and metal interconnection lines 3, pads 5 and contact dots 6 are etched out. ...

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Abstract

The invention relates to a process for producing three-dimension nerve microelectrode, belonging to micro mechanical-electric technical field. The invention comprises using silicon chip as substrate, grows a bottom layer SiO2 at the front face of the silicon chip, forming a metal alloy layer on the bottom layer SiO2 and etching metal interconnecting lines, press welding points and contact round points, then growing a top layer SiO2 at the front face of the bottom layer, using buffer HF acid solution to etch the top layer SiO2, to expose the press welding points and the contact round points, and using photo resist to stuff the press welding points, rotationally coating SU-8 adhesive at the front face of the silicon plane structure of the contact round points, via photo-etching and etching techniques to form a cylinder holes, and using photo resist to stuff the press welding points, plating and growing metal in the cylinder holes, to form metal cylinders, uses development to remove the photo resist in the press welding points to expose the press welding points, and finally washing to obtain three-dimension multi-path microelectrode array. The invention can reduce production cost, improve the height controllability of microelectrode, and improve the consistence of each path.

Description

technical field [0001] The invention relates to a processing method in the field of micro-electromechanical technology, in particular to a method for manufacturing a three-dimensional nerve microelectrode based on a micro-electromechanical processing technology. Background technique [0002] For many patients with severe neurological damage, traditional drug therapy and other methods cannot cure nerve damage. At the same time, nerve repair methods based on artificial electronic devices have been widely studied and applied. As the interface components between artificial electronic devices and biological tissues, neural microelectrodes are playing an increasingly important role in the field of neural repair such as motor function and sensory function. In the study of artificial hearing restoration, microelectrodes implanted in the cochlea are used to directly stimulate the remaining auditory nerve fibers, and send neural electrical signals to the auditory center of the brain t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B81C1/00
Inventor 隋晓红李莹辉任秋实
Owner 上海华实投资有限公司
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