Through-hole etching method

Abstract

A pylome etching method is provided, which comprises: forming pylome etching structure, which includes adhesive coating sedimentary in sequence, etch stop layer, dielectric layer and patterned photoresist layer; etching antireflective coating; etching dielectric layer; eliminating photoresist layer; etching the etch stop layer; The etching process of the said dielectric layer includes the first etching process and the second etching process etched respectively by the first etching gas and the second etching gas. The method provided in the invention can improve the tightness of the photoresist layer to effectively control the appearance of the etching pylome, further adjust the both transverse and lognitudinal etching selection ratio and precisely control the shape of the etching pylome to avoid damage to sidewall of the gird and guarantee the normal operation of the device.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a through hole etching method. Background technique [0002] VLSI (Very Large Scale Integrated Circuit, VLSI) usually requires more than one metal layer to provide sufficient interconnection capacity. The through holes filled with conductive materials are realized, and in order to ensure the stability of the device, there is no electrical connection between the through holes, which makes it very important to strictly control the through hole etching process. With the increasing density of devices and complexity of processes, higher requirements are placed on the via etching process. [0003] 1A to 1E are schematic diagrams illustrating methods for etching through holes in the prior art. In the prior art, etching through holes refers to etching the etching structure of the through holes to obtain the interconnection between multilayer metals and the active par...

AI Technical Summary

Problems solved by technology

Usually, the photoresist layer is soft and vulnerable to damage during the etching process, which is equivalent to changing the design size and causing via hole etching stripe defects. For deep sub-micron process nodes, this via etching stripe Defects can easily cause interconnections between vias, which in turn cause short circuits between metal lines and cause device performance failure

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