Scan chain and method that realizing high speed testing circuitry

Abstract

Boundary scan circuitry that includes a plurality of scan cells that each contain two scan registers each for storing a respective test value. During on-chip or inter-chip testing, one of the scan registers is responsive to a functional clock signal so that the test cell generates transition delay test data having at least one state transition made at the speed of the functional clock signal. The transition delay test data allows the integrity of on-chip functional circuitry or the integrity of inter-chip circuitry to be verified at full functional speed.

Description

technical field [0001] The present invention generally relates to the field of integrated circuits. The invention is particularly directed to scan chain circuits that enable scan testing at functional clock speeds. Background technique [0002] Conventional integrated circuit (IC) scan testing has two main functions. First, in a multi-chip environment, scan testing allows verification of the integrity of inter-die connections. This type of scan testing is commonly referred to as "boundary scan" testing and is the subject of Institute of Electrical and Electronics Engineers (IEEE) Standard 1149.1, the entire contents of which are hereby incorporated by reference for background and contextual information. Second, in a single-chip environment, scan testing allows the functional blocks of an integrated circuit to be isolated from external pins as described in the 1149.1 standard, or boundary-scan around the circuit core inside the chip in the case of the IEEE1500 standard unde...

AI Technical Summary

Problems solved by technology

One disadvantage of conventional boundary-scan circuits is that they do not provide a convenient way to scan functional circuits (e.g., core logic) at their normal operating functional speeds using the scanning capabilities of scan circuit structures such as scan circuit structure 18 of FIG. ) method for performing transition delay test

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