High breakdown voltage semiconductor integrated circuit device and dielectric separation type semiconductor device

A technology of integrated circuits and semiconductors, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of easy accumulation of impurities, difficult oxide films, and inability of semiconductor devices to function, to prevent displacement and achieve high reliability. , Improve the effect of insulation withstand voltage

Active Publication Date: 2007-09-12
HITACHI POWER SEMICON DEVICE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] However, it is very difficult to form a uniform oxide film in deep trenches by CVD
In addition, a large compressive stress is applied to the silicon side due to volume expansion that occurs when the oxide film on the reverse surface that can form a uniform oxide film by a thermal oxidation method is formed, and a displacement (in the low impurity concentration region 610 ) is formed due to the oxidation stress. offset portion), and impurities tend to accumulate on the offset portion, which causes serious problems such as the cause of leakage current
If this problem is not solved, the semiconductor device cannot function

Method used

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  • High breakdown voltage semiconductor integrated circuit device and dielectric separation type semiconductor device
  • High breakdown voltage semiconductor integrated circuit device and dielectric separation type semiconductor device
  • High breakdown voltage semiconductor integrated circuit device and dielectric separation type semiconductor device

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Experimental program
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Effect test

no. 1 approach

[0064] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of a semiconductor integrated circuit device according to this embodiment. In Fig. 1, the symbol 101 represents a silicon support substrate, 102 is a buried oxide film, 103 is an element region, 104 is a buried polysilicon film, 105 is a side oxide film, 106 is a surface oxide film, 107 is a trench, and 108 is n + Dope (dope) region, 109 is p-doped region, 110 is buried n + Doped region, 111 is the side n + Doped region, 112 is polysilicon wiring, 113 is p + doped region. In addition, FIG. 3 shows a plan view of the semiconductor integrated circuit device of the present embodiment. Two element formation regions 103a and 103b are formed adjacent to each other. Polysilicon wiring 112 is formed to straddle trench 107 . Symbol 114 in FIG. 3 represents the first side of the trench. In this embodiment, the structure is adopted: thermal...

no. 2 approach

[0073] FIG. 8 shows a cross-sectional view of the semiconductor integrated circuit device of this embodiment. In this embodiment, a plurality of trenches 107 are formed in the isolation region. In FIG. 8 , the case surrounded by two grooves is illustrated. Usually, although it is designed in such a way that the rated insulation withstand voltage can be obtained with one groove, if multiple grooves 107 are provided, it is possible to greatly reduce the disadvantages generated inside the grooves 107 during the processing process. bad rate.

[0074] FIG. 9 shows changes in the defect rate when the number of grooves is changed. The defective rate is the ratio of the number of measured units whose dielectric withstand voltage dropped by 30% or more based on the average value when measuring the dielectric withstand voltage of 2,000 different integrated circuit devices. From this result, it can be seen that when a plurality of trenches are provided as in the semiconductor integrat...

no. 3 approach

[0076] In the semiconductor integrated circuit device of this embodiment, the thickness of the side oxide film 105 formed in the trench is reduced. If the thickness of the side oxide film 105 is reduced, the stress generated at the interface between silicon oxide and silicon during formation of the side oxide film can be reduced, thereby reducing the defect rate due to defects.

[0077] FIG. 10 shows the relationship between the breakdown voltage ratio and the value obtained by dividing the thickness of the buried oxide film 102 by the thickness of the oxide film 105 on the inner surface of the trench. The defective rate is the ratio of the number of measurement points whose dielectric withstand voltage drops by 30% or more based on the average value when measuring the dielectric withstand voltage of 1000 different integrated circuit devices. From this result, it can be seen that when the value obtained by dividing the film thickness of the buried oxide film 102 by the film th...

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Abstract

It is an object of the present invention to provide an integrated circuit device structured to uniformly apply a voltage to side oxide films formed in a trench at both sides in an SOI substrate.

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit device using an SOI (Silicon On Insulator or Semiconductor On Insulator) substrate and separating elements through a trench (trench), in particular to a semiconductor integrated circuit device for an intelligent power device (intelligent power device), and The present invention relates to a semiconductor device using a dielectric separation method for insulation between elements and a method for manufacturing the same. Background technique [0002] A semiconductor integrated circuit device with components such as transistors and resistors formed on an SOI substrate with a semiconductor layer formed on an insulating film can realize high-speed switching operations on the order of μs or less and high withstand voltages above 100V through the reduction of parasitic capacitance. High reliability of generating lock (latch) and the like. An SOI substrate is described in Patent Document 1, a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/12H01L21/84H01L21/762
CPCH01L21/76264
Inventor 渡边笃雄本田光利石塚典男伊藤昌弘田畑利仁栗田信一神冈秀和
Owner HITACHI POWER SEMICON DEVICE
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