Semiconductor device and method of manufacturing the same
A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as PN junction breakdown, failure to obtain target source-drain withstand voltage, etc., and achieve low on-resistance Effect
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[0033] The structure of the high withstand voltage MOS transistor according to the embodiment of the present invention will be described with reference to FIG. 10 . An N-type epitaxial silicon layer 2 is epitaxially grown on a P-type single crystal silicon substrate 1 , and an N+ type buried silicon layer 3 is formed on the interface between the single crystal silicon substrate 1 and the epitaxial silicon layer 2 . A LOCOS film 4 having a film thickness of about 1000 nm is formed on the epitaxial silicon layer 2 , and a gate electrode 5 is formed on the LOCOS film 4 . On the surface of the epitaxial silicon layer 2 on the left side of the LOCOS film 4, a P-type first drift layer (P+L) 6 is formed, and on the surface of the epitaxial silicon layer 2 on the right side of the LOCOS film, the gate electrode 5 is sandwiched in between. A P+ type source layer (PSD) 7 is disposed facing the first drift layer 6 . An N+ layer (NSD) 8 for setting the epitaxial silicon layer 2 to the so...
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