Total increment adjuster using the high-rank passive network

Abstract

The summation increment regulator based on high-order passive network comprises: a subtracter with minuend input as system input and subtrahend input connected the output of DAC, a decision unit with output connected with DAC input and system output, a 1-bit DAC, and a high-order passive network with input and output corresponding to subtracter output and decision unit input. This invention removes the limit on processing speed led by integration loop, simple and reliable, and consumes less power fit to apply in hyperspeed system.

Description

technical field [0001] The invention relates to a sum incremental modulator using a high-order passive network, and belongs to the technical field of signal processing and communication devices. Background technique [0002] At present, the sum-delta modulator, commonly known as the Σ-Δ modulator, has been widely used in audio coding, fractional frequency synthesis, ADC design, digital power amplifier and other applications, and plays an important role. The sum-delta modulator system used in the prior art still adopts an integrator structure, and it is difficult to realize an ideal integrator in an actual system. Although it is theoretically possible to implement an integrator with an operational amplifier circuit, due to the influence of the non-ideal characteristics of the operational amplifier, especially in the case of ultra-high-speed signal processing, it is also difficult to realize an operational amplifier with close to ideal characteristics. The implementation of t...

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Problems solved by technology

The sum-delta modulator system used in the prior art still adopts the integrator structure, and it is difficult to realize the ideal integrator in the actual system

Although it is theoretically possible to implement an integrator with an operational amplifier circuit, due to the influence of the non-ideal characteristics of the operational amplifier, especially in the case of ultra-high-speed signal processing, it is also difficult to realize an operational amplifier with close to ideal characteristics. Affects the integrator implementation, which significantly degrades the performance of the sum-delta modulator

In order to improve the performance of the sum-delta modulator, the order of the sum-delta modulator can be increased. The conventional second-order or higher-order sum-delta modulator often adopts a double-loop or multi-loop form. Although the second-order or higher-order system is in the The performance has been improved, but the degree of complexity is much greater than that of the first-order system, and the coefficient setting of the system also has relatively high requirements, otherwise it will cause system instability, especially for all parts of the system that have the same speed requirements , it is more difficult to implement in the case of high-speed signal processing

At present, there are still many sum-delta modulators in practical use, which are realized by discrete systems composed of switched capacitor networks. This form of circuit is highly controllable and can achieve high precision, but the delay The switched capacitor network involved in circuits such as circuit breakers still requires a high-gain operational amplifier, so it is also subject to the same limitations as the continuous sum delta modulator in high-speed applications, and the charging and discharging time of a large number of switches and capacitors is also very important. The increase in system speed has greatly limited the

In a word, in the prior art, whether it is a continuous sum delta modulator or a discrete sum delta modulator, due to the high dependence on operational amplifiers, switches and capacitors, the improvement of its signal processing speed has been limited. Significant limitations, affecting the application of sigma-delta modulators in high-speed signal processing systems

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