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Method for optimizing route for exposing wafer

A path optimization and path technology, applied in the field of photolithography, can solve the problems of long exposure time, consumption, affecting the system exposure yield, etc., and achieve the effect of shortening the consumption time and improving the yield.

Inactive Publication Date: 2007-07-25
SHANGHAI MICRO ELECTRONICS EQUIP (GRP) CO LTD
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Problems solved by technology

It can be seen from the figure that the planning method of the "S" shape and "Z" shape exposure path is very simple, only need to scan line by line according to the specified path, but because of this fixed path direction, it is difficult to optimize the time It shows a disadvantage, that is, in general, it takes a long exposure time to adopt these two exposure paths, which affects the exposure yield of the system

Method used

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  • Method for optimizing route for exposing wafer
  • Method for optimizing route for exposing wafer
  • Method for optimizing route for exposing wafer

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Embodiment Construction

[0025] The method for optimizing the wafer exposure path of the present invention will be summarized below.

[0026] First, it is necessary to determine the exposure field distribution and exposure path constraints. The exposure field distribution is determined according to the process parameters of the product with the assistance of the lithography machine process software. The exposure field distribution information mainly includes the center coordinates of each exposure field and the state to be exposed. The purpose of collecting the exposure field distribution information is to Further determine the limitation conditions of the exposure path, and provide reference data for subsequent steps such as scanning and exposure. Exposure path constraints are used to judge the legitimacy of an exposure path, which mainly depends on the measurability of the leveling parameters of the exposure field. Referring to Fig. 2, it has shown the exposure field distribution of a kind of wafer...

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Abstract

A method for optimizing exposure path of wafer includes generating initial exposure path as per limited condition, calculating duty time of said path, storing said path as better path and entering it into circulation, generating new exposure path after partial revision and judging whether said new path is legal one or not as per limited condition, calculating duty time of each legal path when it is generated, comparing duty time of legal path with that of better path and using the one with less duty time as better path, withdrawing from circulation when condition is satisfied.

Description

technical field [0001] The invention relates to photolithography technology, in particular to a method for planning wafer exposure paths. Background technique [0002] The semiconductor chip manufacturing process consists of a series of complex physical and chemical treatment processes on the surface of silicon wafers. Among them, the more important photolithography process, or more specifically, photolithography, is mainly a part of the reticle or semiconductor circuit mask. Or multiple graphics, after being irradiated by exposure light, the optical imaging system will project and transfer the graphics onto the wafer, glass and other substrates coated with photoresist photosensitive materials, and form one or more circuits on the wafer through the subsequent process , and cut it into independent chips (die, the core of the integrated circuit), and finally package the tested chips into product chips. [0003] In the above-mentioned photolithography process, the area exposed...

Claims

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Application Information

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IPC IPC(8): G03F7/20H01L21/027
Inventor 何乐姚名
Owner SHANGHAI MICRO ELECTRONICS EQUIP (GRP) CO LTD
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