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Shallow ditch groove separation process monitoring domain and monitoring method

A technology of shallow trenches and layouts, applied in semiconductor/solid-state device testing/measurement, electrical components, electrical solid-state devices, etc., to achieve space-saving effects

Inactive Publication Date: 2010-02-17
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This method monitors the etching of the trench by introducing a sacrificial layer as a reference layer. However, since the etching process has a large dependence on the density of the trench, when the density of the trench to be etched is different, the etching The etch rate is different, if the process window of the trench isolation cannot be known, the method has great limitations

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  • Shallow ditch groove separation process monitoring domain and monitoring method
  • Shallow ditch groove separation process monitoring domain and monitoring method
  • Shallow ditch groove separation process monitoring domain and monitoring method

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Embodiment Construction

[0039] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0040] When the process size shrinks from 90nm technology node to 65nm technology node, according to the design rule (design rule), the aspect ratio of shallow trench isolation (STI) increases from 3.5 at 90nm to 5 at 65nm. , and the design of the shallow trench isolation density is different for different products, which brings great difficulties to the etching process of the trench and the subsequent deposition and planarization process. How to monitor the process window and process stability of the shallow trench process will also become very important.

[0041] The invention provides a monitoring layout of shallow trench isolation process, which is used to monitor the process window of shallow trench isolation, including: complex g...

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Abstract

The invention relates to a monitoring layout of shallow trench isolation process which is used for monitoring shallow trench isolation process window. The invention comprises a plurality of pattern groups used for monitoring an etching process window. Each pattern group consists of a plurality of line drawings and open drawings of interval distribution. The line drawings are used for forming an active region and the open drawings are used for forming shallow trench isolation; a method applying the monitoring layout of shallow trench isolation process for monitoring the shallow trench isolationprocess includes the following processes: the monitoring layout transforms a trench formed in a semiconductor base through photoetching; a dielectric layer is deposited in the trench and is flatted;the etched, deposited and flatted semiconductor base is respectively cut to form a section, which can monitor the shallow trench isolation process window which is etched, deposited and processed through chemical mechanical polishing.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a monitoring layout and a monitoring method of a shallow trench isolation process. Background technique [0002] With the decreasing size of semiconductor devices, especially when entering the technology node of 65nm or even smaller, the structure of the device has more and more influence on the manufacturing process, which makes the monitoring of the manufacturing process more important. As the size of the device decreases, the process window becomes smaller, and process stability is difficult to control, which makes process maintenance more difficult. Taking Shallow Trench Isolation (STI) as an example, when the process size is reduced from 90nm technology node to 65nm technology node, according to the design rule (design rule), its aspect ratio (aspect ratio) increases from 3.5 at 90nm to 65nm 5, that is to say, the depth of the trench is about 5 times the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544H01L21/66
Inventor 刘明源
Owner SEMICON MFG INT (SHANGHAI) CORP
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