Nonvolatile semiconductor memory device and read method

A storage device, non-volatile technology, applied in information storage, static memory, read-only memory, etc.

Active Publication Date: 2009-05-06
异基因开发有限责任公司
View PDF7 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Furthermore, when the same memory cell is repeatedly read and the read operation is performed, in the worst case, there is a possibility that the stored data will completely disappear and cannot be read.
[0024] Furthermore, in a memory cell array composed of 1R type memory cells, since the read voltage is also applied to the selected memory cells other than the read target memory cells sharing the word line or bit line with the read target memory cells, the above-mentioned read disturbance phenomenon more obvious

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Nonvolatile semiconductor memory device and read method
  • Nonvolatile semiconductor memory device and read method
  • Nonvolatile semiconductor memory device and read method

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0076]Fig. 8 shows an example of the configuration of the device of the present invention. In addition, in FIG. 8 , the parts common to those of the conventional nonvolatile semiconductor memory device will be described with common reference numerals. As shown in FIG. 8, the device of the present invention has a bit line decoder 16, a word line decoder 17, and a voltage switch circuit 22a around a memory cell array 15 in which 1R type memory cells (not shown) are arranged in a matrix. , the readout circuit 23 and the control circuit 20a. Basically, the configuration is the same as that of a conventional nonvolatile semiconductor memory device having a memory cell array of 1R type memory cells shown in FIG. 5 . The difference from the conventional nonvolatile semiconductor memory device of FIG. 5 lies in the voltage applied from the voltage switch circuit 22a to the memory cell array 15 and its timing operation and the operation of the control circuit 20a for controlling the o...

Embodiment 1

[0083] First, referring to Figure 9 and Figure 10 In the first embodiment, in order to perform a data read operation, a read voltage is applied to a selected memory cell, and then a dummy read voltage for suppressing a change in resistance of the selected memory cell is applied.

[0084] In Figure 9 and Figure 10 2 shows the sequence of applying voltages to each part during an example data read operation of the memory cell array 15 of the device of the present invention.

[0085] First, when reading the data of the selected memory cell, the selected word line connected to the selected memory cell is maintained at the ground potential Vss, and the read period Tr is applied to the other non-selected word lines and all the bit lines. Voltage V1. In the read period Tr, since a voltage difference of the read voltage V1 is generated between the selected word line and the selected bit line, the variable resistance element of the selected memory cell flows a read current correspon...

Embodiment 2

[0089] Second, referring to Figure 9 and Figure 11 In the second embodiment, in order to perform a data read operation, a read voltage is applied to a selected memory cell, and then a dummy read voltage for suppressing a change in resistance of the selected memory cell is applied. At this time, a voltage V2 having a voltage value twice the voltage V1 is supplied to the voltage switch circuit 22a of the device of the present invention shown in FIG. 8 .

[0090] In Figure 9 and Figure 11 2 shows the sequence of applying voltages to each part during an example data read operation of the memory cell array 15 of the device of the present invention.

[0091] First, when reading the data of the selected memory cell, the selected word line connected to the selected memory cell is maintained at the ground potential Vss, and the read period Tr is applied to the other non-selected word lines and all the bit lines. Voltage V1. In the read period Tr, since a voltage difference of the ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

This device comprises a memory cell selecting circuit 17 for selecting the memory cell from the memory cell array 15 in units of row, column or memory cell, a read voltage application circuit 22a for applying a read voltage to the variable resistor element of the selected memory cell selected by the memory cell selecting circuit 17, and a read circuit 23 for detecting the amount of the read current flowing in accordance with the resistance value of the variable resistor element with respect to the memory cell to be read of the selected memory cells and reading the information stored in the memory cell to be read. The read voltage application circuit 22a applies a dummy read voltage having reversed polarity from the read voltage to the variable resistor element of the selected memory cell.

Description

technical field [0001] The present invention relates to a semiconductor memory device having a memory cell array in which a plurality of memory cells including variable resistance elements which store information using changes in resistance are arranged in a row direction and a column direction respectively, and more specifically relates to preventing and A technique for suppressing the deterioration of the quality of stored data accompanying the read operation of a memory cell array. Background technique [0002] In recent years, FeRAM (Ferroelectric RAM: ferroelectric RAM), MRAM (Magnetic RAM: magnetic Resistor RAM) and OUM (Ovonic Unified Memory: phase-change memory) and other device structures have launched fierce development competition in terms of high performance, high reliability, low cost, and process matching. [0003] In addition, for these prior technologies, Shangquing Liu and Alex Ignatiev of the University of Houston in the United States have disclosed a meth...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/06G11C16/26G11C7/00
Inventor 川添豪哉玉井幸夫岛冈笃志森本英德粟屋信义
Owner 异基因开发有限责任公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap