Insulated gate semiconductor device with stripe widths

Abstract

There is disclosed an insulated gate bipolar transistor which includes a p type semiconductor region (11) formed in a surface of an n- semiconductor layer (3) by double diffusion in corresponding relation to a p type base region (4) of an IGBT cell adjacent thereto, and an emitter electrode (9) formed on and connected to the p type semiconductor region (11) through a contact hole (CHP) having a width (Wch2) which is greater than a width (Wch1) of a contact hole (CH1), thereby preventing device breakdown due to latch-up by the operation of a parasitic thyristor during an ON state and during an ON-state to OFF-state transition even if main and control electrodes in an active region are reduced in size.

Description

BACKGROUND OF THE INVENTION1. Field of the InventionThe present invention relates to an insulated gate semiconductor device such as an insulated gate bipolar transistor (referred to as an IGBT hereinafter) and a method of fabricating the same.2. Description of the Background ArtAn insulated gate semiconductor device comprises a plurality of p type and n type semiconductor layers alternately joined together in series such that the semiconductor layers at opposite ends are electrically, connected to positive and negative main electrodes, respectively, and at least one of the other semiconductor layers is joined to a gate electrode applying an electric field through an insulator.<Construction of Background Art Device>in general, an IGBT comprises a multiplicity of IGBT elements (referred to as IGBT cells hereinafter) connected in parallel. FIG. 32 is a cross sectional view showing a basic structure of an IGBT cell forming the IGBT.Referring to FIG. 32, a p.sup.+ semiconductor lay...

AI Technical Summary

Benefits of technology

In the insulated gate semiconductor device according to the present invention, the width of the main electrodes formed on the upper surface of the fourth semiconductor layer adjacent the active region is greater than the main electrodes within the active region, thereby to increase the amount of carrier current flowing into the main electrodes and reduce the amount of carrier current concentrated on the main electrodes within the active region adjacent the fourth semiconductor layer, preventing device breakdown due to operation of the parasitic thyristor when the device is on and changes from the ON state to OFF state. If the main electrodes and control electrodes are reduced in size in the active region, the main electrodes formed on the upper surface of the fourth semiconductor layer adjacent the active region can be wide, to reduce the amount of carrier current concentrated on the main electrodes within the active region adjacent the fourth semiconductor layer and prevent device breakdown due to operation of the parasitic thyristor.

It is an object of the present invention to provide an insulated gate transistor which is prevented from being broken down due to latch-up.

Problems solved by technology

The breakdown due to latch-up is considered to be liable to occur at specific positions of the IGBT.

This also results in IGBT breakdown.