Method and apparatus for generating circuit model for static noise analysis

Abstract

A method and apparatus for generating a noise circuit model for an electronic circuit includes analyzing the electronic circuit to determine a first circuit parameter for a victim and aggressor circuits and a second circuit parameter for the aggressor circuits, ordering the aggressor circuits based on their first and second circuit parameters, setting a current model parameter of the circuit model to an initial value, selecting a first aggressor circuit, determining whether to reduce the selected aggressor circuit into a virtual attacker model based on its first circuit parameter, updating the current model parameter in accordance with either the selected aggressor circuit or its virtual attacker model to be inserted, inserting either the selected aggressor circuit or its virtual attacker model to the circuit model, for each aggressor circuit.

Description

FIELD OF THE INVENTION[0001]The present invention relates to circuit verification. More particularly, the present invention relates to a method and apparatus for generating a circuit model for noise analysis.BACKGROUND OF THE INVENTION[0002]The size and complexity of integrated circuits (IC) has made conventional circuit simulation methods too computationally expensive to use for circuit verification. For example, conventional circuit reduction methods based on Asymptotic Waveform Evaluation and other algorithms have provided a good accuracy / speed trade-off, and have been used extensively in recent years for timing and noise analysis. However, because of the inherently large size and complexity of the circuit, even these techniques to create circuit models alone are too computationally expensive for analysis of an entire microprocessor.[0003]For noise analysis, component circuits (nets) in a circuit under simulation (referred to as a noise circuit) is classified into two types of ne...

AI Technical Summary

Problems solved by technology

The size and complexity of integrated circuits (IC) has made conventional circuit simulation methods too computationally expensive to use for circuit verification.

However, because of the inherently large size and complexity of the circuit, even these techniques to create circuit models alone are too computationally expensive for analysis of an entire microprocessor.

Since the time for analyzing a circuit using reduction methods is roughly proportional to the number of nodes in the circuit cubed i.e., (number of nodes)3, analysis of such a large circuit would require an impracticably long run time.

Spending a large amount of execution time analyzing a noise circuit with excessively large aggressor nets does not necessarily increase the accuracy of the analysis.

That is, simpler models result in shorter run time, but it is typically at the expense of increased pessimism.

In addition, the conventional virtual attacker approach only considers the aggressor's effect on noise when selecting virtual attackers.

However, there are cases where a victim net is coupled to a large number of small, weakly coupled aggressors, and a few large, strongly coupled aggressors.

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