Piggybacking of ECC corrections behind loads

Abstract

An apparatus including circuitry configured to detect and correct an ECC error in a non-targeted portion of a load access to a first data in a memory. An ECC error check circuit is configured to convey a first indication in response to detecting an error in a non-targeted first portion of the first data. A microcode unit is coupled to receive the first indication that the ECC check circuit has detected the ECC error and in response to the indication dispatch a first microcode routine stored by the microcode unit. The first microcode routine includes instructions which, when executed, correct the ECC error in the first portion. Correction of the error in the first portion does not include cancellation of data corresponding to the load access.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]This invention is related to the field of processors and computer systems and, more particularly, to error correction code (ECC) mechanisms in processors and computer systems.[0003]2. Description of the Related Art[0004]Modern processors are more frequently being designed to offer improved reliability features. For example, reliability features are often demanded in large computing systems such as servers. Generally, reliability features reduce the likelihood that erroneous operation of the processor, or software executing thereon, causes erroneous operation of the system as a whole. At the same time, semiconductor fabrication technology improvements continue to shrink the size of the circuits used to form processors. The smaller circuitry, and the more dense packing of circuits made possible by the reduced size, increases the possibility that so-called “soft” errors may be experienced by the processor. Generally, a sof...

AI Technical Summary

Benefits of technology

[0013]A method and mechanism are contemplated which reduce the probability of an error in load data. An apparatus is contemplated which includes circuitry configured to detect and correct ECC errors in non-targeted portions of load access data without the delays inherent in a cancellation, correction, and rebroadcast of load data. The apparatus includes an ECC error check circuit which is configured to detect an error in a non-targeted first portion of data corresponding to a data access to memory. In response to the detection, the ECC error check circuit is configured to convey a first indication. A microcode unit is coupled to receive an indication corresponding to the first indication and dispatch a first microcode routine stored by the microcode unit. The first microcode routine includes instructions which, when executed, correct the ECC error in the first portion. Correction of the error in the first portion does not include cancellation of data corresponding to the load access. In one embodiment, the load access may be initiated by a load / store unit and include byte enables which indicate those portions of the load data which are relevant to the particular load operation.

Problems solved by technology

Generally, reliability features reduce the likelihood that erroneous operation of the processor, or software executing thereon, causes erroneous operation of the system as a whole.

The smaller circuitry, and the more dense packing of circuits made possible by the reduced size, increases the possibility that so-called “soft” errors may be experienced by the processor.

Generally, a soft error is an error caused by the occurrence of an event, rather than a defect in the circuitry itself (which produces a “hard” error).

Soft errors are intermittent, whereas hard errors occur repeatedly and predictably.

Soft errors may occur due to an excessive amount of noise near a circuit, random alpha particles striking the circuit, etc.

If the changed bits are subsequently accessed, the erroneously changed values may propagate, eventually causing erroneous operation on a larger scale (e.g. reduced reliability of the processor as a whole or reduced reliability of the system including the processor as a whole).

If the parity doesn't match the accessed set of data bits, then an error is detected.

However, while utilizing parity bits may enable detection of errors, parity bits do not provide the ability to correct these errors.

An “uncorrectable ECC error” is an ECC error in which the error is detected but the bits in error are not identifiable and thus the error cannot be corrected.

The ECC data is also stored in the memory or another memory provided for storing ECC data, and thus the ECC data itself is subject to possible error.

However, if an ECC error is detected, the previously broadcast data must be canceled, the data corrected, and the correct data rebroadcast.

As the example above illustrates, ECC errors may delay the completion of a load by several cycles.

Additionally, canceling of the first data broadcast may result in a scheduler having to cancel all operations which are dependent on this load data and reissuing them.

However, such an approach extends the load pipeline and is not a desirable solution, especially because ECC errors may not be very common.

However, utilizing this approach, the scrubber may end up working on one part of the cache while load accesses are going to a different part of the cache and still hitting the ECC errors.

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