Device for compensating for a test temperature deviation in a semiconductor device handler
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Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. FIG. 1 is a schematic plan view of a handler having a device for compensating a test temperature deviation in accordance with the invention. FIGS. 2A and 2B are schematic side sectional views of a test site of the handler of FIG. 1.
The handler and its operation will be explained as follows.
The handler shown in FIG. 1 includes a loading unit 10 in a front portion of the handler 1, in which user trays may be loaded, and an unloading unit 20 to one side of the loading unit 10, in which tested semiconductor devices may be loaded on the user trays, with the tested semiconductor devices classified according to a result of the test(s).
Buffer units 40 are provided on both sides of a middle position of the handler 1. The buffer units 40 temporarily retain the semiconductor devices transported from the loading unit 10. An exchange unit 50 is provide...
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