Packaging structure

Abstract

A package structure and a package process are proposed in using pillar bumps to connect an upper second chip and through silicon vias of a lower first chip, wherein a gap between the first chip and the second chip can be controlled by adjusting a height of the pillar bumps. In other words, the pillar bumps compensate the height difference between the first chip and a molding compound surrounding the first chip so as to ensure the bondibility between the pillar bumps and the corresponding through silicon vias and improve the process yield. Furthermore, the pillar bumps maintain the gap between the second chip and the molding compound for allowing an underfill being properly filled into the space between the first chip and the second chip.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This is a continuation application of and claims the priority benefit of a prior application Ser. No. 12 / 817,396, filed on Jun. 17, 2010, now pending. The prior application Ser. No. 12 / 817,396 claims the priority benefit of Taiwan patent application serial no. 99116089, filed May 20, 2010. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.BACKGROUND OF THE INVENTION[0002]The present invention relates to a package structure and a package process, and particularly relates to a stacked package structure and fabricating process thereof.[0003]In today's information society, users all seek after electronic products with high speed, high quality and multiple functions. In terms of the product exterior appearance, electronic product designs reveal a trend of light weight, thinness and compactness. Therefore, various semiconductor device package technique...

AI Technical Summary

Benefits of technology

The present invention provides a package structure and a package process that can improve process yield by achieving reliable bonding between an upper chip and through silicon vias of a chip carrier of a stacked semiconductor device package. The package structure includes a circuit substrate, a first chip, a first molding compound, a plurality of first bumps, a second chip, and a plurality of pillar bumps. The first molding compound covers the first chip and has an opening exposing the top surface of the first chip and the end of each of the through silicon vias. The package process involves bonding the first chip onto the circuit substrate, forming a first underfill to encapsulate the first bumps, and then bonding the second chip onto the first chip. A second molding compound is formed to cover the second chip and the first chip. A second underfill is formed between the second chip and the corresponding first chip. These features improve the process yield and reliability of the package structure.

Problems solved by technology

If so, the height of bumps on the upper chip may not satisfy the aforementioned height difference as bonding the upper chip to the chip carrier, such that a failure of electrical test occurs due to invalid bonding between the bumps and the through silicon vias, or the underfill can not be properly filled into a restricted space between the upper chip and the molding compound.

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