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Three-dimensionally integrated semicondutor device and method for manufacturing the same

a semiconductor and three-dimensional technology, applied in semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of complex structure of devices, difficulty in forming large amounts of wiring on the post electrode side, and need similar facilities, so as to improve the performance of rf (radio frequency) modules, improve high-frequency characteristics, and reduce the installation area.

Inactive Publication Date: 2011-03-17
NAT UNIV CORP KYUSHU INST OF TECH (JP)
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0012]According to the present invention, planar integration can be readily changed to three-dimensional integration, and signal paths (an LSI chip—a wiring substrate—circuit elements) can be shortened in order to improve high-frequency characteristics. Thus, the performance of an RF (radio frequency) module can be improved, and the installation area thereof can be reduced, whereby high density mounting and enhancement of the performance of small-sized electronic equipment such as cellular phones become possible. The high density mounting can reduce the size and cost of equipment.
[0013]Furthermore, according to the present invention, the side surfaces of the post electrodes can be exposed. Therefore, solder fillets can be formed on the side surfaces, whereby the mounting strength can be increased considerably.

Problems solved by technology

Although a conventional typical module technique can form multilayer wiring on the side toward the substrate of a package so as to increase the amount of wiring, in general, the conventional technique encounters difficulty in forming a large amount of wiring on the post electrode side.
However, the illustrated semiconductor device has a complicated structure, and requires a complicated process especially for a connection structure for establishing connection between the wiring patterns provided on the wiring substrate and the mother substrate, respectively.
; that is, requires facilities similar to those used in the former stage, and cannot be performed by use of only conventional facilities for the latter stage.

Method used

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  • Three-dimensionally integrated semicondutor device and method for manufacturing the same
  • Three-dimensionally integrated semicondutor device and method for manufacturing the same
  • Three-dimensionally integrated semicondutor device and method for manufacturing the same

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first embodiment

[0036]The present invention will now be described by way of example. the three-dimensionally integrated semiconductor device of the present invention will be described with reference to FIGS. 1 to 8. FIG. 1 is a view showing a state in which a semiconductor chip (LSI chip) is bonded and connected to the back face of a wiring substrate (multilayer organic substrate). Notably, in the following description, the upper side of the wiring substrate in FIG. 1 on which the LSI chip is mounted will be referred to as the back face (first main face), and the lower side of the wiring substrate in FIG. 1 on which another circuit element is mounted as will be described later will be referred to as the front face (second main face). In the illustrated example, the LSI chip is bonded to the upper side (as viewed in FIG. 1) of the multilayer organic substrate by use of a die bond material, and is connected to the uppermost wiring pattern of the organic substrate via bonding wires. Metal pad portions...

second embodiment

[0053]FIG. 11 is a plan view showing an example in which the semiconductor device of the second embodiment is used. FIG. 12 is a side cross-sectional view showing one of semiconductor modules A to C shown in FIG. 11. As shown in FIGS. 11 and 12, the semiconductor modules A to C and circuit elements such as capacitors are disposed on the wiring pattern of the mother substrate, and are electrically and mechanically connected thereto by means of soldering or the like. At that time, as shown in FIG. 12, solder fillets (the shape of solder surface formed at a connection portion after solidification of solder) are formed such that meniscuses (the shape formed by the surface of liquid when the surface deforms into a curved shape due to force such as surface tension) are formed on the side surfaces of the post electrodes exposed to the side surfaces of the resin seal, whereby connection strength can be increased.

[0054]Next, a third embodiment of the present invention will be described with ...

fifth embodiment

[0056]FIG. 17 is a view for describing the present invention. After the circuit element IC is attached to the front face of the wiring substrate (organic substrate) as shown in FIG. 13, as in the case of the back face side, a wiring-added post electrode component as shown in FIGS. 2(A) to 2(C) is attached to the front face side. After that, as in the above-described example, the front face side is resin-sealed, and the support plate is separated. After that, various circuit elements (resistances R and capacitors C) are flip-chip-bond-connected to the front face wiring traces. As a result, a semiconductor device in which circuit elements are stacked in three tiers can be fabricated. By means of stacking another wiring-added post electrode component, circuit elements can be connected in four or more tiers.

[0057]FIG. 18(A) is a perspective view showing a wiring-added post electrode component different from that shown in FIGS. 2(A) to 2(C), FIG. 18(B) is a cross-sectional view of the wi...

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PUM

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Abstract

A wiring substrate has, on each of opposite faces thereof, connection pad portions to which various circuit elements are connected, and wiring traces for connecting the connection pad portions. The wiring substrate also has a through wiring portion for establishing mutual connection between the connection pad portions and the wiring traces on the front face and those on the back face. A post electrode component is formed such that it includes a plurality of post electrodes supported by a support portion. A semiconductor chip is attached to the back face of the wiring substrate, and is connected to the connection pad portions on the back face. After the post electrode component is fixed to and electrically connected to the wiring traces at predetermined positions, and resin sealing is performed, the support portion is separated so as to expose end surfaces of the post electrodes or back face wiring traces connected thereto. Another circuit element is disposed on the front face of the wiring substrate, and is connected to the connection pad portions on the front face.

Description

TECHNICAL FIELD[0001]The present invention relates to a three-dimensionally integrated semiconductor device in which various circuit elements, including a semiconductor chip, are attached to opposite faces of a wiring substrate, and to a method for manufacturing the same.BACKGROUND ART[0002]High-frequency characteristics are very important for an RF (radio frequency) module or the like used in cellular phones. The High-frequency characteristics of such a module are most sensitively affected by wiring between terminals of a semiconductor (LSI) chip and external components. Conventional wiring is long; i.e., each wiring line extends through LSI chip bonding wire, a package substrate, and a post electrode to a terminal of a component. In the case of an RF module, although the amount of wiring within the module is large, it is sufficient for the module to have a small number of external connection terminals. Although a conventional typical module technique can form multilayer wiring on ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/48H01L21/50
CPCH01L21/486H01L21/568H01L2924/01079H01L24/48H01L2924/19105H01L2924/19041H01L2225/06582H01L2225/06517H01L2225/0651H01L21/6835H01L23/3121H01L23/49805H01L23/49827H01L23/5389H01L25/0657H01L25/16H01L25/50H01L2221/68359H01L2221/68363H01L2221/68386H01L2224/16225H01L2224/32225H01L2224/48227H01L2224/73265H01L2924/00H01L2924/00012H01L24/73H01L2924/14H01L2924/181H01L2924/15183H01L2924/00014H01L2224/45099H01L2224/45015H01L2924/207
Inventor ISHIHARA, MASAMICHI
Owner NAT UNIV CORP KYUSHU INST OF TECH (JP)
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