Systems and methods for a turbo low-density parity-check decoder
a parity-check decoder and low-density technology, applied in the direction of redundant data error correction, coding, code conversion, etc., can solve the problems of low probability of data bits d being lost in transmission, the ldpc technique cannot guarantee the transmission perfectness, and the loss of information in transmission, etc., to achieve high efficiency, reduce the number of parity node processors, and limit complexity
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BRIEF DESCRIPTION OF THE DRAWINGS
[0020]Features, aspects, and embodiments of the inventions are described in conjunction with the attached drawings, in which:
[0021]FIG. 1 is a diagram illustrating an example communication system that uses LDPC codes;
[0022]FIG. 2 is a diagram illustrating the operation of an exemplary parity check matrix;
[0023]FIG. 3 is a illustrating the operation of an exemplary parity node processor;
[0024]FIG. 4 is a diagram illustrating the operation of an exemplary variable node processor;
[0025]FIG. 5 is a diagram illustrating an example exponential matrix configured in accordance with one embodiment;
[0026]FIG. 6 is a diagram illustrating an example parity check matrix in accordance with one embodiment;
[0027]FIG. 7 is a diagram illustrating an example sub-matrix used to construct the parity check matrix of FIG. 6 in accordance with one embodiment;
[0028]FIG. 8 is a diagram illustrating further sub-matrices used to construct the parity check matrix of FIG. 6 in ...
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