Processor executing SIMD instructions
a technology of simd instruction and processor, applied in the field of processor, can solve the problems of inability to evaluate the results of such comparisons in a single instruction, inability to make a judgment on whether all values of these four flags are zero, and existing processors cannot fully satisfy a wide range of requirements concerning media processing, etc., to achieve faster repetitions of data reshuffling, facilitate programming, and speed up the effect of speed
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example 1
[0134] mov r1, 0x23;
[0135] This instruction description indicates that only an instruction “mov” shall be executed.
example 2
[0136] mov r1, 0x38
[0137] add r0, r1, r2
[0138] sub r3, r1, r2;
[0139] These instruction descriptions indicate that three instructions of “mov”, “add” and “sub” shall be executed in parallel.
[0140] The instruction control unit 10 identifies an issue group and sends it to the decoding unit 20. The decoding unit 20 decodes the instructions in the issue group, and controls resources required for executing such instructions.
[0141] Next, an explanation is given for registers included in the processor 1.
[0142] Table 1 below lists a set of registers of the processor 1.
TABLE 1Register nameBit widthNo. of registersUsageR0˜R3132 bits32General-purpose registers. Used as datamemory pointer, data storage and the likewhen operation instruction is executed.TAR32 bits1Branch register. Used as branch addressstorage at branch point.LR32 bits1Link register.SVR16 bits2Save register. Used for saving condition flag(CFR) and various modes.M0˜M164 bits2Operation registers. Used as data storage(MH0:ML...
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