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Processor executing SIMD instructions

a technology of simd instruction and processor, applied in the field of processor, can solve the problems of inability to evaluate the results of such comparisons in a single instruction, inability to make a judgment on whether all values of these four flags are zero, and existing processors cannot fully satisfy a wide range of requirements concerning media processing, etc., to achieve faster repetitions of data reshuffling, facilitate programming, and speed up the effect of speed

Inactive Publication Date: 2008-02-21
TANAKA TETABUYA +8
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0009] As is obvious from the above explanation, the processor according to the present invention is capable of executing a characteristic SIMD instruction for judging whether or not results of operations performed under a SIMD compare instruction are all zero and setting such results to condition flags. This allows a faster extraction of results of SIMD compare instructions (especially, agreement / disagreement of results), as well as a faster comparison processing to be performed on more than one pixel value as a processing unit and a faster detection of the EOF (End Of File) of a file.
[0023] As described above, the processor according to the present invention is capable of performing sophisticated SIMD operations and a wide range of digital signal processing required for multimedia processing at a high speed, and is capable of being employed as a core processor to be commonly used in mobile phone, mobile AV device, digital television, DVD and other devices, the processor according to the present invention is extremely useful in the present age in which the advent of high-performance and cost effective multimedia apparatuses is desired.

Problems solved by technology

However, there is a problem that such existing processors do not fully satisfy a wide range of requirements concerning media processing.
For example, although capable of operating on multiple data elements in a single instruction and comparing multiple data elements in a single instruction, the existing processors cannot evaluate the results of such comparisons in a single instruction.
However, it cannot make a judgment on whether all values of these four flags are zero or not in one instruction.
This requires a plurality of instructions for evaluating results every time a comparison is made against another set of pixel values when four pixel values are used as a unit of comparison, resulting in an increased number of instructions and therefore a decreased speed of image processing.

Method used

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  • Processor executing SIMD instructions
  • Processor executing SIMD instructions
  • Processor executing SIMD instructions

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0134] mov r1, 0x23;

[0135] This instruction description indicates that only an instruction “mov” shall be executed.

example 2

[0136] mov r1, 0x38

[0137] add r0, r1, r2

[0138] sub r3, r1, r2;

[0139] These instruction descriptions indicate that three instructions of “mov”, “add” and “sub” shall be executed in parallel.

[0140] The instruction control unit 10 identifies an issue group and sends it to the decoding unit 20. The decoding unit 20 decodes the instructions in the issue group, and controls resources required for executing such instructions.

[0141] Next, an explanation is given for registers included in the processor 1.

[0142] Table 1 below lists a set of registers of the processor 1.

TABLE 1Register nameBit widthNo. of registersUsageR0˜R3132 bits32General-purpose registers. Used as datamemory pointer, data storage and the likewhen operation instruction is executed.TAR32 bits1Branch register. Used as branch addressstorage at branch point.LR32 bits1Link register.SVR16 bits2Save register. Used for saving condition flag(CFR) and various modes.M0˜M164 bits2Operation registers. Used as data storage(MH0:ML...

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Abstract

A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

Description

[0001] This application is a divisional of application Ser. No. 10 / 668,358, filed Sep. 24, 2003.BACKGROUND OF THE INVENTION [0002] (1) Field of the Invention [0003] The present invention relates to a processor such as a DSP and a CPU, and more particularly to a processor suitable for performing signal processing for sounds, images and others. [0004] (2) Description of the Related Art [0005] With the development in multimedia technologies, processors are increasingly required to be capable of high-speed media processing represented by sound and image signal processing. As existing processors responding to such requirement, there exist Pentium (R) / Pentium (R) III / Pentium 4 (R) MMX / SSE / SSE2 and others produced by the Intel Corporation of the United States supporting SIMD (Single Instruction Multiple Data) instructions. Of them, MMX, for example, is capable of performing the same operations in one instruction on a maximum of eight integers stored in a 64-bit MMX register. [0006] However...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F9/38G06F7/00G06F9/00G06F9/30G06F9/302G06F9/305
CPCG06F9/30014G06F9/30021G06F9/30025G06F9/30167G06F9/30094G06F9/30145G06F9/3016G06F9/30036G06F9/38
Inventor TANAKA, TETSUYAOKABAYASHI, HAZUKIHEISHI, TAKETOOGAWA, HAJIMESUZUKI, TSUNEYUKIKIYOHARA, TOKUZOTANAKA, TAKESHINISHIDA, HIDESHIMAEDA, MASAKI
Owner TANAKA TETABUYA
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