Dual trench isolation for CMOS with hybrid orientations

Abstract

The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

Description

RELATED APPLICATIONS [0001] This application is related to co-pending and co-assigned U.S. patent application Ser. No. 10 / 799,380, filed Mar. 12, 2004, Ser. No. 10 / 696,634, filed Oct. 29, 2003, and Ser. No. 10 / 250,241, filed Jun. 23, 2003, the entire contents of each application are incorporated herein by reference.FIELD OF THE INVENTION [0002] The present invention relates to high-performance metal oxide semiconductor field effect transistors (MOSFETs) for digital and analog applications, and more particular to MOSFETs utilizing carrier mobility enhancement from surface orientation in which a dual trench isolation design is employed. Specifically, a first trench isolation region having a first depth is used to isolate nFETs from pFETs, while second trench isolation regions having a second depth, which is shallower than the first depth, are used to isolate nFETs from nFETs and pFETs from pFETs. BACKGROUND OF THE INVENTION [0003] In present semiconductor technology, complementary met...

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Benefits of technology

[0013] The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other.

Problems solved by technology

To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. pFETs having larger widths are undesirable since they take up a significant amount of chip area.

Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces.

As can be deduced from the above discussion, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices.

Thus, it has become more difficult to obtain void- and seam-free trench fill.

In general, isolation for the latter, including nFET and pFET isolation and latch-up, consumes much more chip area and requires much deeper STI depth.

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