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Debugger apparatus and debugging method

Inactive Publication Date: 2005-02-10
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0003] Therefore, a main object of the present invention is to provide a debugger apparatus capable of efficiently writing an instruction in an E-memory, controlling an overhead resulting from transfer traffic, and efficiently supplying the instruction to a CPU, while controlling an area increase.

Problems solved by technology

Problems in the foregoing process are, if an inter-chip delay is large, because the system LSI and the ICE are different chips, itis not possible to emulate the instruction; incorporating the ICE in the system LSI invites an increase in area; the use of the built-in memory results in a shortage of capacity; a built-in ROM cannot be debugged in the case of downloading the monitor program from an external ROM; and an instruction-incorporated ROM cannot be emulated.

Method used

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  • Debugger apparatus and debugging method
  • Debugger apparatus and debugging method

Examples

Experimental program
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embodiment 1

[0114] Embodiment 1

[0115] As shown in FIG. 1, a system LSI 101 comprises a CPU 110, ROM 111, selector 112, emulation memory execution supervision unit 113, serial transmission / reception unit 114, first emulation memory 115, and second emulation memory 116. Hereinafter, the emulation memory execution supervision unit is abbreviated to execution supervision unit, the serial transmission / reception unit to transmission / reception unit, the first emulation memory to first E-memory, and the second emulation memory to second E-memory. A host PC (hereinafter, abbreviated to host) 102 is a computer, wherein a debugger software capable of serial transmission and reception with respect to the transmission / reception unit 114 is installed.

[0116] As shown in FIG. 2, the execution supervision unit 113 comprises a first address selector 121, a first address converter 122, first comparison device 123, first address register 124, second address selector 125, second address converter 126, second compa...

embodiment 2

[0147] Embodiment 2

[0148] In the embodiment 1, when there is an unconditional branch instruction prior to a final line of the memory capacity of an E-memory, the destination of the transferred instruction sequence is, without using the entire region of the E-memory, switched over to the other E-memory. In doing so, the overhead resulting from the traffic in transferring the instructions is generated. An embodiment 2 of the present invention deals with the inconvenience. In the embodiment 2, FIG. 1 is incorporated therein by reference.

[0149] As shown in FIG. 4, an E-memory execution supervision unit 113a comprises a first address / byte number register 136 in place of the first register 124 in the embodiment 1 (FIG. 2), and a second address / byte number register 138 in place of the second register 128 therein. In the description below, the first address / byte number register is abbreviated to first register, and the second address / byte number register to second register. The first and s...

embodiment 3

[0170] Embodiment 3

[0171] In the embodiment 2, even when the branch destination of the unconditional branch instruction of the instruction sequence 1 fits into the same E-memory, the instructions from the branch destination onwards are written in the other E-memory as the instruction sequence 2. Because of that, the overhead resulting from the transfer traffic increases. An embodiment 3 of the present invention deals with the inconvenience. In the embodiment 3, FIGS. 1 and 4 are incorporated therein by reference.

[0172]FIG. 6 shows instruction sequences including the unconditional branch instruction, the branch destination of which is present in the E-memory.

[0173] 1. Operation of Writing Instruction in E-Memory

[0174] The host traces the instructions, from the starting instruction, according to the execution sequence to thereby judge whether or not the branch destination corresponds to the memory region of the first E-memory 115 in the presence of the unconditional branch instruct...

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Abstract

A debugger apparatus according to the present embodiment comprises a host, CPU, a plurality of E-memory units (emulation memory units) for storing instructions, and an execution supervision unit. The host traces the instructions to be stored in the E-memory units and transfers the tracing result in the form of an instruction sequence. The execution supervision unit is connected to the CPU, E-memory units, and host. The execution supervision unit individually writes the instruction sequences transferred from the host in the plurality of E-memory units, reads an instruction sequence from one of the plurality of E-memory units in accordance with an instruction address of the CPU to thereby transfer the instruction sequence to the CPU, and outputs an instruction rewriting order to the host when the instruction address of the CPU is irrelevant.

Description

BACKGROUND OF THE INVENTION [0001] The present invention relates to a debugger apparatus configured in the manner that an instruction supplied to a system LSI of a host PC is temporarily stored in an E-memory (emulation memory) to be thereafter supplied from the E-memory to a CPU. [0002] In an in-circuit emulator (ICE), which is an example of a conventional debugger apparatus, a debug monitor program is written in a built-in memory such as a cash memory, and the instruction for the CPU is emulated. Problems in the foregoing process are, if an inter-chip delay is large, because the system LSI and the ICE are different chips, itis not possible to emulate the instruction; incorporating the ICE in the system LSI invites an increase in area; the use of the built-in memory results in a shortage of capacity; a built-in ROM cannot be debugged in the case of downloading the monitor program from an external ROM; and an instruction-incorporated ROM cannot be emulated. SUMMARY OF THE INVENTION ...

Claims

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Application Information

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IPC IPC(8): G06F11/36G06F13/00G06F19/00
CPCG06F11/3652G06F11/3636
Inventor MORIKAWA, TORUWATANABE, KAZUHIDEMIYAJI, SHINYA
Owner PANASONIC CORP
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