A MOS FET tube and its manufacturing method

Abstract

This invention discloses one MOS field effect tube and its process method, which has the following steps: a, injecting well ion and annealing and sacrifice oxidation layer for peeling off; b, growing or depositing one layer of grating oxidation layer; c, totally etching middle area grating oxidation; d, growing film grating oxidation; e, the current process method steps are applicable for this invention.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a MOS field effect transistor and a manufacturing method thereof. Background technique [0002] A cross-sectional structure diagram of an existing MOS field effect transistor is shown in FIG. 1 . In MOS field effect transistors, there will be parasitic capacitance between the gate-drain / source. As shown in FIG. 2, the parasitic capacitance includes gate to drain overlap capacitance (hereinafter referred to as C ovl ) and gate todrain fringing capacitance (hereinafter referred to as C fringing ). In the conventional semiconductor manufacturing process flow of the prior art, the thickness of the gate oxide under the gate is generally uniform, and the parasitic capacitance of the MOS field effect transistor with the existing structure is usually relatively large. Parasitic capacitance usually affects the speed performance of digital circuits. The larger the capacitance, ...

AI Technical Summary

Problems solved by technology

But the above approach is at the expense of reducing the intrinsic performance of the transistor

[0003] The parasitic capacitance between the gate-drain / source of the MOS field-effect transistor produced by the method of the prior art, such as the gate-drain overlapping capacitance and the gate-drain edge capacitance is relatively large, which will affect the speed performance of the digital circuit

Images