Semiconductor memory

Abstract

A semiconductor memory using a DLL circuit having a phase comparison circuit for comparing phases of an internal clock and a delay clock and a variable delay addition circuit for adjusting delay amount according to a signal from the phase comparison circuit comprises a means for inputting a first signal latched to a logic "1" by start of one clock cycle of the internal clock to the variable delay addition circuit through a dummy delay at the start of burst and a means for detecting the duration time of the logic "1" of the first signal inputted by the variable delay addition circuit through the dummy delay until one clock cycle of the internal clock is completed and setting the initial value of delay amount of the variable delay addition circuit based on the duration time.

Description

technical field [0001] The present invention relates to a semiconductor memory, especially a flash memory, which ensures synchronization of an external clock and a DQ output (memory data output) even at a high-speed clock. Background technique [0002] In recent years, the demand for flash memory has rapidly expanded as a nonvolatile memory. Under such circumstances, the speed-up of the reading speed is progressing, and it is urgently required to operate at a clock frequency exceeding 100 MHz for practical use. Therefore, even in a flash memory, a structure for canceling an internal clock delay becomes indispensable. So far, although there is no structure targeting flash memory, various DLL (Delay Locked Loop: Delay Locked Loop) circuits are provided or proposed (for example, refer to Patent Document 1). [0003] Patent Document 1: JP-A-2001-326563 [0004] Next, the necessity of the DLL circuit will be described with reference to FIG. 17 . FIG. 17 ...

AI Technical Summary

Problems solved by technology

[0013] However, in the current flash memory standard, it is necessary to output DQ at several clocks from the synchronous read, and there is a problem that the conventional DLL circuit such as the above-mentioned DLL circuit cannot meet this standard.

Alternatively, in order to meet the current flash memory specifications, it is conceivable to input an external clock even during backup and perform phase correction in the DLL circuit at all times, but this will cause a problem that the power consumption will increase unnecessarily.

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