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Phase locked loop fast lock method

A phase-locked loop and phase technology, applied in the field of phase-locked loops, can solve the problems of reducing frequency offset accuracy and other issues

Active Publication Date: 2007-02-14
ZARLINK SEMICON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0017] Phase noise (drift and jitter) on the measured reference can degrade the accuracy of the measured frequency offset

Method used

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Embodiment Construction

[0043] In general, the method disclosed in this patent to reduce settling time and improve output clock quality during settling includes the following steps: estimating a new frequency offset, ramping an integrator to the new frequency offset, phase compensation or phase pulling , the decay time interval, and switching to higher bandwidth and / or lower damping to allow PLL tuning.

[0044] Figure 4 A PLL according to the teachings of the present invention is illustrated. The phase and frequency detector 100 outputs to an adder 110 and a register 112 which is controlled by a control unit 114 . The output of the register 112 is connected to the adder 110 . Register 112 is a preferred embodiment of the phase compensation circuit described in detail below. The output of the adder 110 is connected to a comparator 118 . The output of adder 110 is also connected to a pair of multipliers 120, 180 which introduce P and I factors, respectively. The multiplier 120 is connected to th...

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Abstract

The present invention is a method for quickly locking a Type II phase-locked loop (PLL) without degrading the output signal in large quantities after a frequency jump. The method disclosed herein to reduce settling time and improve output clock quality during settling includes the steps of estimating the new frequency offset with a separate circuit outside the PLL loop to accurately measure the frequency of the input signal. Ramp up the integrator to the new frequency offset. Perform phase compensation or phase pulling. When edge-to-edge alignment is required, the remaining phase offset is compensated. Conversely, the residual phase offset is pulled while disabling the integrator in the PLL loop filter. Reduce bandwidth and / or reduce damping to allow PLL tuning. Switch the PLL to the final bandwidth and damping required by the application.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of US Provisional Patent Application 60 / 703,285, filed July 28, 2005, which is incorporated herein by reference. technical field [0003] The invention relates to a phase-locked loop, in particular to a method for realizing locking in a relatively short time. Background technique [0004] One of the characteristics of a phase-locked loop (PLL) is the lock or setup time; that is, the time it takes for the PLL to lock to an input signal or to respond to frequency and phase jumps. In general, the lock time depends on the loop bandwidth of the PLL, the lower the loop bandwidth, the longer it takes for the PLL to lock. In the art, one generally defines the term "adjustment" as to within some relative or absolute precision. [0005] PLLs are not only used in telecom applications, but also in measurement technology (such as optical long-distance measurement), motor control, medical equipm...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/08H03L7/093H03L7/18
CPCH03L7/095H03L7/107H03L7/12H03L7/113Y10S331/02H03L7/1075
Inventor 缅诺·杰尔德·斯皮耶克贾森·罗伯特·罗辛斯基罗伯特斯·劳伦丘斯·范德·瓦尔克
Owner ZARLINK SEMICON LTD
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