Equiphase multi-phase clock signal generator circuit and serial digital data receiving circuit using the same

Abstract

The invention provides an equal-phase multi-phase clock signal generating circuit. The purpose is to minimize the increase in the number of components, to suppress the increase in the area of ​​the semiconductor substrate-like circuit and the increase in power consumption, and to make the duty ratio of the output equal-phase multi-phase clock signal constant independently of the duty ratio of the input clock signal . In the equal-phase multi-phase clock signal generation circuit of the present invention, the input clock signal is converted into a complementary clock signal which has been divided by 2, and then input to a complementary voltage-controlled delay element column. Since the frequency of the input clock signal is divided by 2, the frequency-divided complementary clock signal becomes a clock signal having a constant duty ratio independent of the duty ratio of the input clock. By inputting the frequency-divided complementary clock signal to the voltage-controlled delay element column, and phase-comparing the complementary output signal from the voltage-controlled delay element column with the frequency-divided complementary clock signal, it is possible to output a signal synchronized with the above-mentioned input clock. Equiphase multiphase clock signal.

Description

technical field [0001] The present invention relates to a serial digital data receiving circuit, and more particularly to an equal-phase multi-phase clock signal generating circuit using a DLL (delay locked loop) circuit used in the serial digital data receiving circuit. Background technique [0002] In the receiving circuit of high-speed serial digital data in recent years, when demodulating digital data, it is generally adopted: use an equal-phase multi-phase signal synchronous with the period of the transmission clock signal N times the number of serialized symbol bits. The way the symbol sample signal of the clock signal samples serial digital data. [0003] In a receiving circuit using such a method of sampling serial digital data using an equiphase multiphase clock signal synchronized with the cycle of the transmission clock signal, in order to generate an equiphase multiphase clock, a combination of phase and frequency comparators is generally used. A phase-locked lo...

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Problems solved by technology

[0019] However, when the input clock is divided by N, in order to output the same phase difference as in the case of no frequency division, an M×N phase clock must be generated, so it is necessary to prepare N times the complementary voltage control delay element of the DLL circuit. column, the circuit scale naturally increases, and in order to realize the desired circuit, it is necessary to increase the circuit area on the semiconductor substrate and consume power

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