Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device comprises a semiconductor substrate having an through hole, a first insulation resin layer formed on an inner surface of the through hole, a second insulation resin layer formed on at least one of front and rear surfaces of the semiconductor substrate, and a first conductor layer formed in the through hole to connect at least both front and rear surfaces of the semiconductor substrate and insulated from the inner surface of the through hole with the first insulation resin layer. A second conductor layer (wiring pattern) which is electrically connected to the first conductor layer in the through hole is further provided on the second insulation resin layer. The conductor layer formed in the through hole and constituting a connecting plug has a high insulation reliability. Therefore, a semiconductor device suitable for a multi-chip package and the like can be obtained. Further, since the forming ability of the conductor layer connecting the front and rear surfaces and the insulation layer is high, the manufacturing cost can be reduced.

Description

technical field [0001] The present invention relates to a semiconductor device suitable for a multi-chip package on which a plurality of semiconductor elements (semiconductor chips) are mounted, and a method for manufacturing the same. Background technique [0002] In recent years, in order to achieve miniaturization and high-density mounting of semiconductor devices, a stacked multi-chip package in which a plurality of semiconductor elements (chips) are stacked and sealed in one package has been realized. In general, in a stacked multi-chip package, electrical connection between each electrode pad of a plurality of semiconductor chips and an electrode portion of a substrate has been performed by means of wire bonding. In addition, when connecting a plurality of semiconductor chips to each other, electrode pads of the respective semiconductor chips are electrically connected by wire bonding. [0003] Like such a stacked multi-chip package, a package structure in which wire ...

AI Technical Summary

Problems solved by technology

[0007] However, the SiO mentioned above 2 layer, Si 3 N 4 It is technically difficult to uniformly form an inorganic insulating layer such as a layer on the inner surface of a through-hole, and in particular, there is a problem that it is difficult to form a thick film.

As mentioned above, the inorganic insulator layer formed by using the existing semiconductor process becomes the main factor that reduces the insulation reliability of the connection plug connecting the front and back sides of the semiconductor chip.

[0008] In addition, in the case where the inorganic insulator layer is formed on the inner surface of the through hole, it is technically difficult to fill the inside of the through hole with a conductor such as metal.

In this regard, it is conceivable to form a conductive layer only on the wall surface of the through hole as in the usual formation of the through hole, but in this case, the problem of lowering the mechanical strength of the semiconductor chip will arise.

Images