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Data processing device with microprocessor and with additional arithmetic unit and associated method

A technology of data processing device and arithmetic unit, which is applied in the direction of electrical digital data processing, special data processing application, register device, etc., and can solve problems such as delay

Inactive Publication Date: 2006-01-11
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] A disadvantage of these known integrated circuits with a microprocessor and an additional arithmetic unit is that after execution of a processing step or a processing cycle by the additional arithmetic unit, the microprocessor must reload the registers with new values ​​for at least some of the new operands, With this then the next processing cycle begins
[0010] The disadvantage of implementing EP0822482A2 is that each additional register bank requires chip surface area as a function of register bank size
[0011] Moreover, according to the prior art, the microprocessor must start each single calculation by asserting the corresponding control bit, which may cause further delays

Method used

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  • Data processing device with microprocessor and with additional arithmetic unit and associated method
  • Data processing device with microprocessor and with additional arithmetic unit and associated method
  • Data processing device with microprocessor and with additional arithmetic unit and associated method

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Embodiment Construction

[0032] exist Figure 2 to Figure 5 In the same or similar embodiments, elements or features, the same reference numerals are provided.

[0033] figure 2 A first exemplary embodiment of a data processing device 100 is shown having a microprocessor 90 and having an additional special arithmetic unit 40 for special calculations which would be too costly if performed by the microprocessor 90. time.

[0034] Arithmetic unit 40 is coupled to microprocessor 90 via a plurality of registers, wherein in principle a first register is used for controlling data transfers and a second register is used for sending commands. Furthermore, the arithmetic unit 40 is associated with a control register 50 connected to a control logic circuit 60 .

[0035] In particular, the special feature of the data processing apparatus 100 according to the first exemplary embodiment is that registers can be loaded from a peripheral memory 10 in the form of an EEPROM (Electrically Erasable Programmable Read-...

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Abstract

In order to further develop a data processing device (100; 100') having at least one microprocessor (90) and having at least one additional arithmetic unit (40) as well as a method of performing at least one particular defined calculation by means of the data processing device (100; 100') in such a way that a plurality of calculations may be performed in sequence without any intervention by the microprocessor (90), it is proposed that the registers be loadable from at least one in particular peripheral memory (10), for example from at least one R[andom]A[ccess]M[emory], from at least one R[ead]O[nly]M[emory] or from at least one E[lectrically] E[rasable] P[rogrammable] R[ead]O[nly]M[emory.

Description

technical field [0001] The invention relates to a data processing device with at least one microprocessor and with at least one additional arithmetic unit, and to a method for performing at least one specifically defined calculation with at least one data processing device of the type described above. Background technique [0002] Such a data processing device, in particular a data processing device integrated in a single semiconductor chip, is known in principle, for example, from the data sheet of the integrated circuit P83C852 manufactured by Philips. [0003] The integrated circuit is installed in particular in a portable card-type data carrier, for example in a test card format, and is used, for example, to encrypt data using an asymmetric encryption method or to decrypt such data. In such instances, the data block is specifically indexed by a key index modulo a constant, where the constant has a large number of digits, to achieve the most secure possible encryption. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38G06F9/302G06F9/30G06F9/32G06F17/00
CPCG06F9/325G06F9/3012G06F9/383
Inventor T·贝林R·马扎恩
Owner NXP BV
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