Multiplier calculating modular multiplicatin of large numbers

Abstract

A multiplier of large number modulo multification is prepared as connecting REPC control unit to two write - read control ports of double port SRAM and able control port of REDC data channel separately for write - read control and calculation control; using double port synchronous random storage SRAM to store operation number of A, B, N and R in algorithm as well as intermediate result and final result of operation; using data channel to obtain data from two data write - read ports of double SRAM for finalizing operation of multification and addition of large number in algorithm.

Description

technical field [0001] The invention relates to an operation circuit, in particular to a large number modular multiplication calculation multiplier which can be applied in the field of encryption; it belongs to the field of circuit technology. Background technique [0002] Public key encryption algorithms are widely used in the information field (such as network security). The public key encryption algorithm requires the user to have two keys, one public key, which can be used by everyone, to encrypt the plaintext sent to the specified user; the other secret key, which the user can use to decrypt the ciphertext. A prerequisite of the public key algorithm is that it is almost impossible to derive the secret key from the public key. [0003] The RSA cryptosystem based on the difficulty of large number factorization is the most famous public key encryption method, and its key steps are: given non-negative integers M, e, N, calculate R=M e mod N(0<=E, M<N), obviously, t...

AI Technical Summary

Problems solved by technology

[0030] The prior art scheme adopts 4 groups of 2048-bit registers to store binary numbers A, B, N, R respectively, and two groups of 2048-bit adders are used to realize the addition operation in the algorithm. Its disadvantages: one needs a large number of register units; If it is 2048 bits, then (2048x4=8196) register units are needed. When FPGA or ASIC chip realizes the above-mentioned circuit, the increase of the number of registers will cause the circuit area to be large, the circuit power consumption is high, and the circuit cost is high

[0031] The second is that the technical solution is not easy to expand. With the improvement of public key encryption security, the number of bits of the modulus N also increases. If the modulus N increases to 4096 bits, the required register unit is doubled, reaching (4096x4=16392 ) register units

The circuit area will also be doubled accordingly, and the power consumption will also be doubled accordingly

[0032] The third is that when the technical solution is actually applied, some circuits will be idle, resulting in waste

If the design is aimed at modulo N being 2048 bits, and in actual application, modulo N may be 1024 bits (modulo N is optional between 0-2048bis in actual application), at this time the other 1024 bits of the circuit will be in an idle state, forming big waste of resources

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