High-density chip scale package and method of manufacturing the same
A chip-size packaging and high-density technology, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve problems such as limiting the scope of application
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[0051] Figures 3a to 3i A cross-sectional view showing a process of manufacturing a high-density chip-scale package using a heat radiation structure according to a preferred embodiment of the present invention, wherein a die is mounted on the package by wire bonding techniques.
[0052] Figure 3a is a cross-sectional view of a copper-clad thin laminate 301, which is a substrate used in the high-density chip-scale package of the present invention. Such as Figure 3a As shown, the insulating layer 303 is covered with copper foil 302 . There are various copper clad thin laminates. However, a glass / epoxy resin copper-clad thin laminate composed of a reinforcing material obtained by infiltrating an epoxy resin (a mixture of a resin and a hardener) into glass fibers and copper foil is mainly used. In particular, copper-clad thin laminates designated FR-4 are most commonly used. An FR-4 copper-clad thin laminate is used as the copper-clad thin laminate in the present invention,...
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