Semiconductor memory device having advanced data strobe circuit

Abstract

A data strobe circuit for prefetching M number of N bit data, N and M being a positive integer, includes a data strobe buffering unit for generating N number of align control signals based on a data strobe signal; a synchronizing block having M number of latch blocks, each for receiving N bit data and outputting the N-1 bit data in a parallel fashion in response to N-1 number of the align control signals and one bit prefetched data in response to the remaining align control signals; and a output block having M number of aligning blocks, each for receiving the N-1 bit data in the parallel fashion, synchronizing the N-1 bit data with the align control signal and outputting the synchronized N-1 bit data as the N-1 bit prefetched data.

Description

technical field [0001] The present invention relates to a semiconductor memory device, in particular to a data strobe pulse circuit in the semiconductor memory device which has more time margins in data write operation. Background technique [0002] Generally, in double data rate synchronous dynamic random access memory (hereinafter referred to as DDR SDRAM), a method of prefetching 2-bit data or 4-bit data has been used to increase the operation speed of DDR SDRAM. However, since the time margin is small when DDR SDRAM prefetches individual bits of multi-bit data according to the prior art, some serious problems arise. Therefore, in order to increase the operation speed of DDR SDRAM, the method of prefetching multi-bit data is considered as a limiting condition. [0003] FIG. 1A is a block diagram of a data strobe circuit of a DDR SDRAM in the prior art, and FIG. 1B is a circuit diagram of a divided first / second data block 160 in the data strobe circuit of a DDR SDRAM in t...

AI Technical Summary

Problems solved by technology

Therefore, a shorter period of the external clock CLK, ie 1tCK, makes each alignment data have a shorter timing margin, ie 0.5tCK; so the data strobe circuit in the prior art is not suitable for semiconductor memory using high frequency High-speed operation of the device

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