A flash controller for asic and its control method

Abstract

A FLASH controller for ASIC and its control method, the controller includes a main control module, and an arbitration module connected with the main control module, read data fifo and write data fifo; the read data fifo and write data fifo All are connected with the arbitration module and the data interface module, wherein the data interface module is connected to the AHB data bus; the controller also includes a register module, and the register module is connected to the read data fifo, the write data fifo, the arbitration module and the configuration interface module, and the configuration interface The module is connected to the AHB configuration bus, and the main control module is connected to the register module through the synchronization module. The present invention uses two sets of bus interfaces of AHB data bus and AHB configuration bus to correspond to different operations, completes FLASH general-purpose read and write operations through DMA data transmission and a large-capacity internal cache unit, simplifies the operation process of the controller, and improves data transmission efficiency.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a FLASH controller for ASIC and a control method thereof. Background technique [0002] With the rapid development of FLASH technology, more and more devices support double-edge-triggered data transmission of the clock signal, that is, Double transfer Rate, abbreviated as DTR. The FLASH transmission rate using DTR technology is twice that of the single-edge data transmission technology. At present, the highest speed of the launched SPI NOR FLASH device in DTR mode has reached 200MHz. In relatively low-frequency logic chip on-chip storage applications, NOR FLASH devices can provide high-speed data transfer rates with a small number of interfaces and support on-chip execution, namely eXecute In Place, abbreviated as XIP. [0003] Application No. 201811314760.4, the patent title is a Chinese patent for a configurable and efficient embedded Nor-FLASH control...

AI Technical Summary

Problems solved by technology

However, these two clocks will also increase the risk of metastability after the signal crosses the clock domain, and in the case of a FLASH controller controlling 2 pieces of FLASH to transmit data with large bandwidth, an eight-wire Octal SPI is usually required to transmit data, then you need Delay processing of 8 data lines, which increases the area and power consumption of the logic unit

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