Pellicle

Abstract

To facilitate the estimation of the delay time between an input and an output. Inverters INV1 and INV4 generate a reference signal R and a signal to-be-corrected H on the basis of an input positive-logic signal Pin and an input negative-logic signal Nin. Since the reference signal R is transferred through a wiring line Lp, it undergoes no delay in the process of the transfer. On the other hand, the signal to-be-corrected H undergoes the influence of the reference signal R and has its phase corrected by a NAND circuit 11 and a NOR circuit 12.

Description

technical field [0001] The present invention relates to a timing adjustment circuit, a drive circuit, an electro-optical device, and an electronic device for generating an output positive logic signal and an output negative logic signal in which the phase difference between an input positive logic signal and an input negative logic signal is reduced. Background technique [0002] Among electronic circuits, there are circuits that perform signal processing using a positive logic signal that becomes active at a high level and a negative logic signal that inverts it. As a representative circuit, there is a shift register that shifts an input pulse using a clock signal and inverting the order of the clock signal. [0003] In such an electronic circuit that operates using two-phase signals, it is desirable that there is no delay between the positive logic signal and the negative logic signal. However, there are many cases where a delay occurs between the two signals due to the g...

AI Technical Summary

Problems solved by technology

[0004] In addition, even if positive logic signals and negative logic signals can be generated without delay between signals, if the wiring distance or path from the generating circuit to the circuit using these signals is different, it will be affected by the wiring capacity, and one signal will be relatively different from the other. one side signal delay

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