Cache line flush micro-architectural implementation method ans system

Abstract

A system and method for flushing a cache line associated with a linear memory address from all caches in the coherency domain. A cache controller receives a memory address, and determines whether the memory address is stored within the closest cache memory in the coherency domain. If a cache line stores the memory address, it is flushed from the cache. The flush instruction is allocated to a write-combining buffer within the cache controller. The write-combining buffer transmits the information to the bus controller. The bus controller locates instances of the memory address stored within external and intel cache memories within the coherency domain; these instances are flushed. The flush instruction can then be evicted from the write-combining buffer. Control bits may be used to indicate whether a write-combining buffer is allocated to the flush instruction, whether the memory address is stored within the closest cache memory, and whether the flush instruction should be evicted from the write-combining buffer.

Description

technical field [0001] The present invention relates generally to computer architecture, and in particular to a system and method that allows a processor to flush cache lines associated with linear memory addresses from all caches in a contiguous domain. Background technique [0002] A cache memory device is a small, fast memory that can be used to store the most frequently accessed data (or "words") from a larger, slower memory. [0003] Dynamic Random Access Memory (DRAM) provides high-capacity storage at low cost. Unfortunately, DRAM access is too slow relative to modern microprocessors. A cache that offers a cost-effective solution provides a static random access memory (SRAM) cache, or a cache that is physically installed on the processor. Even though the cache memory has a relatively small storage capacity, it still enables high-speed access to the data stored therein. [0004] The principle of operation of the cache memory is described below. When an instruction o...

AI Technical Summary

Problems solved by technology

The problem with current systems is that high bandwidth between the cache memory and system memory is required to accommodate the copying of the write-join memory and the write-back memory

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