Non-volatile memory with float gate wall and its preparing process

Abstract

A method for preparing a non-volatile memory with float grid and spacing wall includes such steps as generating the first material layer for providing part of float grid, generating L1 layer with exposed side wall, and generating a spacing wall on said side wall for providing the another part of float grid. Said non-volatile memoryc contains a float grid, an insulating layer surrounding the sides of float grid, and a control grid on the float grid.

Description

(1) Technical field [0001] The invention relates to a semiconductor technology, in particular to a non-volatile semiconductor memory. (2) Background technology [0002] figure 1 It is a cross-sectional view of a traditional non-volatile semiconductor memory. The field oxide region 134 is used to isolate the active area 120 and other active areas in the silicon substrate 130, and a gate is formed on the active area 120. oxide layer (gate oxide) 140, and then deposit a polysilicon layer 150 on the gate oxide layer 140, after patterning, a floating gate (floating gate) will be formed on each active region 120, Then an insulating layer 160 is formed on the floating gate (such as an ONO layer, which is composed of a silicon dioxide layer, a silicon nitride layer and another silicon dioxide layer), and then a polysilicon layer is deposited. 170, patterned into a control gate (control gate), please refer to the paper "A 0.67um2Self-Aligned Shallow Trench" written by S.Aritome et ...

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Problems solved by technology

[0003] The field oxide layer 134 is formed using a known LOCOS process, and the field oxide region 134 and the active region 120 are formed using a different photomask from the floating gate 150 formed later, because the misalignment of the photomask is considered Therefore, the floating gate 150 is partially overlapped with the field oxide region 134. The overlapping portion ("wings") 150W of the floating gate 150 increases the size of the memory, but thus improves the performance of the floating gate 150 and the field oxide region 134. Capacitive coupling between control gates 170

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