LPDDR wafer RDL design method suitable for multi-chip failure analysis

Abstract

The invention discloses an LPDDR wafer RDL design method suitable for multi-chip failure analysis, and belongs to the field of semiconductor packaging, and the method comprises the following steps: S1, based on a conventional LPDDR RDL design, adding a bonding welding position; s2, designing a packaging substrate, and adding a plurality of substrate front golden fingers for DIE connection; s3, packaging is carried out, the bonding welding positions are connected with the golden fingers on the front face of the substrate, S4, resistance is measured, the DIE state is judged through resistance testing, and design is completed. When the original RDL wiring is designed, the following RDL wiring is synchronously added; an unclosed square-shaped wire and two bonding pads (proper positions need to be found for the windowing positions of the bonding pads, and RDL wiring of an original product is not affected) are additionally arranged around the periphery of the DIE, whether the DIE cracks or not is judged through measurement data of wire resistance, a special testing machine is not needed, and the cost is reduced. The cracking of a certain DIE in the multi-chip stack can be judged only by using a universal meter or a simple test device to test the resistor.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to an LPDDR wafer RDL design method suitable for multi-chip failure analysis. Background technique [0002] LPDDR is widely used in mobile consumer electronic products such as mobile phones and tablets, and the internal chip particles are packaged in a multi-layer stacking mode. In the actual production process, when the LPDDR wafer is stacked in a multi-layer package, an RDL will be done before wiring, and then packaging processes such as grinding, cutting, and chip stacking will be performed. The process of multi-layer stacking is relatively difficult, and it is prone to the problem of failure caused by single DIE cracking. [0003] In the existing technical solution, there are often multiple (2 to 8) DIEs with a thickness of only 200um to 40um stacked vertically inside an LPDDR package chip. Once a certain DIE cracks and fails, conventional testing machines canno...

AI Technical Summary

Problems solved by technology

The process of multi-layer stacking is relatively difficult, and it is prone to the problem of failure caused by cracking of a single DIE

[0003] In the existing technical solutions, there are often multiple (2 to 8) DIEs with a thickness of only 200um to 40um stacked vertically inside an LPDDR package chip. Once a certain DIE cracks and fails, conventional testing machines cannot tell which one it is. If there is a problem with DIE, it is necessary to use a special test machine and a special program for testing to distinguish which chip is abnormal, and it is also necessary to develop a special program for analysis

[0004] The failure analysis of multi-layer packaging products requires the use of special testing machines and special programs to test which chip is abnormal. This kind of special machine is expensive, and special programs need to be specially developed for analysis, and it takes a long time. The cost of use is too high, which affects the cost and efficiency of failure analysis

Images