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A layout design method of a multi-type chip and a chip and terminal prepared therefrom

A layout design and multi-model technology, which is applied to the layout design method and the chips prepared therefrom, and the terminal field, can solve the problems of low efficiency of multi-type chip layout design, reduce the probability of secondary cutting, reduce the labor sufficiency, and ensure cutting. The effect of efficiency

Active Publication Date: 2022-07-08
成都复锦功率半导体技术发展有限公司
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Problems solved by technology

[0005] The purpose of the present invention is to overcome the problem of low layout design efficiency of multi-type chips in the prior art, and provide a method for layout design of multi-type chips and the chips and terminals prepared therefor.

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  • A layout design method of a multi-type chip and a chip and terminal prepared therefrom
  • A layout design method of a multi-type chip and a chip and terminal prepared therefrom
  • A layout design method of a multi-type chip and a chip and terminal prepared therefrom

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Embodiment Construction

[0051] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0052] In the description of the present invention, it should be noted that "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated direction or positional relationship is based on the direction or positional relationship described in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific...

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Abstract

The invention discloses a layout design method of a multi-type chip and a prepared chip and a terminal, which belong to the technical field of semiconductors. Under the constraints of the cutting unit parameters, determine the size relationship between the chip size parameters and the corresponding initial cell thresholds, and adjust the chip cell thresholds; calculate the proportional relationship between the corresponding chip cell thresholds and the chip size parameters, and then output the layout design. The present invention first adjusts the chip unit thresholds by different types of chips, and can quickly divide the overall layout into multiple independent operation areas, and then further calculates the proportional relationship between chips and chip units, and then quickly arranges the corresponding number of chips on the corresponding chip units. Within a certain threshold range, the layout design can be flexibly adjusted according to the customer's own chip design parameters simply and quickly, and the layout design can be output efficiently.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a layout design method of a multi-model chip and a chip and a terminal prepared therefrom. Background technique [0002] The layout design of integrated circuits plays a crucial role in the design process of silicon-based semiconductors, and is an important intermediate link in the circuit design and the driving process. Multi-customer wafer layout design is a routine business in the daily production of foundry companies. It is generally composed of multiple customers' tape-out requirements. There are various types of chips, and the number of requirements varies greatly. Under the premise of taking into account time efficiency and finished product yield, There is a certain difficulty in wafer layout design compatible with multiple customers. How to let layout design engineers quickly feedback the intuitive and accurate technical details about the final layout design requi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/392H01L27/02G06F113/18
CPCG06F30/392H01L27/0207G06F2113/18Y02P90/30
Inventor 不公告发明人
Owner 成都复锦功率半导体技术发展有限公司
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