Method and device for constructing power consumption prediction model, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a method and device for constructing a power consumption prediction model and a storage medium, and the method comprises the steps: operating each training program in a training program set, and recording the operation data of each training program, the operation data comprises a count value of each preset performance event when each training program is operated, a power consumption value of a processor when each training program is operated, and an operation duration of each training program; performing iterative calculation according to the operation data of each training program and a preset model scale n, and when an iteration termination condition is reached, obtaining n target performance events selected from the preset performance events and model parameters corresponding to the n target performance events; and constructing a power consumption prediction model according to the n target performance events and the model parameters corresponding to the n target performance events. According to the embodiment of the invention, the power consumption value of the processor can be timely and accurately obtained on the basis of not increasing a hardware unit.

Description

technical field [0001] The present invention relates to the field of communication technology, in particular to a method for constructing a power consumption prediction model, a device for constructing a power consumption prediction model, an electronic device and a storage medium. Background technique [0002] Power consumption is one of the most important considerations in processor design today. Although the processor power consumption can be reduced by reducing the clock frequency. However, blindly reducing the clock frequency cannot really achieve the purpose of reducing power consumption, because running at a low frequency may lead to an increase in the time for the system to process tasks, but instead increases power consumption as a whole. [0003] Dynamic Voltage and Frequency Scaling (DVFS) is a low-power technology that sets the operating voltage and clock frequency according to the actual power consumption of the chip, which can ensure that the provided power me...

AI Technical Summary

Problems solved by technology

However, blindly reducing the clock frequency cannot really achieve the purpose of reducing power consumption, because running at a low frequency may increase the time for the system to process tasks, but instead increase power consumption as a whole

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