Field programmable gate array (FPGA) interconnection resource test algorithm based on graph reinforcement learning

Abstract

The invention belongs to the field programmable gate array (FPGA) testing technology, and particularly relates to an FPGA interconnection resource testing algorithm based on graph reinforcement learning. According to the method, the defect of the existing FPGA interconnection resource testing method based on reinforcement learning and deep reinforcement learning is overcome, namely the defect that the neural network does not have mobility is overcome. According to the method, hidden features of an interconnected resource graph are extracted by means of a graph neural network, a deep reinforcement learning optimization configuration strategy is utilized, and the method is called graph reinforcement learning. The method has mobility and universality, the trained convergence neural network can be applied to generation of interconnection resource test configuration vectors of any FPGA chip, and meanwhile the method can be adopted for all FPGA chips. According to the method, the testing cost of the FPGA interconnection resources is low, specialists do not need to manually find the testing configuration, meanwhile, the converged neural network can be rapidly applied to interconnection resource testing of any FPGA chip, and the process of generating the FPGA testing configuration is completely automatic.

Description

technical field [0001] The invention belongs to FPGA testing technology, in particular to an FPGA interconnection resource testing algorithm based on graph reinforcement learning. Background technique [0002] Field Programmable Gate Array (Field Programmable Gate Array, hereinafter referred to as FPGA), as an important member of digital integrated circuits, because FPGA has rich logic resources, fast and flexible programmability, and perfect automated integrated development environment, It is widely used in many aspects of integrated circuit design and development. However, with the increasing integration of FPGA, the internal structure becomes more complex, and the interconnection resource network required to achieve flexible programmability becomes larger. The proportion of interconnection resource area in the entire chip continues to increase. The failure rate of resources also increases. The engineering community's demand for FPGA internal interconnection resource tes...

AI Technical Summary

Problems solved by technology

[0006] The wiring generation method of the traditional interconnect resource test is mainly aimed at specific chip structure characteristics, relies on expert knowledge, and mainly relies on manual wiring configuration. This test method has low test efficiency, heavy configuration workload, low coverage rate, and does not have universal characteristics, the test time is too long, and often cannot meet the test requirements of today's ultra-large-scale chips

In recent years, some general-purpose FPGA testing methods have emerged with the help of machine learning algorithms, which are methodologically versatile, but in this method, the transferability of the neural network is very poor, that is, the network needs to be retrained for different FPGA chips.

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