Clock path information generation method and device, electronic equipment and medium

Abstract

The invention provides a clock path information generation method and device, electronic equipment and a medium. Through a preset clock path information generation tool, the problem of rapid development of clock network circuits for different large-scale SoC chips is solved. Specifically, clock network information is imported into a clock path information generation tool (an implementation carrier is a script language, such as a Perl language), and clock path code information (such as a Verilog hardware description language) and clock path block diagram information are automatically generated by utilizing the clock path information generation tool, so that an efficient and error-free SoC chip clock network is quickly realized. The SoC chip development time can be greatly shortened, and the design efficiency is improved.

Description

technical field [0001] The present disclosure relates to the field of computer technology, and in particular to a clock path information generation method, device, electronic equipment and media. Background technique [0002] SoC (System on Chip, system-on-chip) is one of the main directions of integrated circuit development at present, and with the development of process node technology of integrated circuits, the circuit integration degree of a single SoC chip is greatly increased, and the processing performance of the chip is also increasing. Among them, the operating frequency of the SoC chip is a key factor in the processing performance of the chip, and the operating frequency is determined by the internal operating clock of the chip. In large-scale SoC integrated circuits, the data transmission of almost all sequential elements is controlled by clock synchronization. The clock frequency determines the speed of data processing and transmission, and the clock frequency i...

AI Technical Summary

Problems solved by technology

Moreover, the code form of the clock circuit is generally realized by connecting and building special clock units instead of using behavior-level syntax style for design, which makes the design of the clock circuit very cumbersome and has a high error rate.

The existing clock network circuits for SoC chips are mainly written by engineers to manually describe the code, and the clock network designs of different SoC chips cannot be reused

This design method has a long design cycle time, and due to manual design, it is inevitable that there will be problems with code syntax and logic functions, which will further prolong the entire SoC chip design and development cycle.

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