CML clock frequency dividing circuit, secondary clock frequency dividing circuit and analog-to-digital converter

Abstract

One embodiment of the invention provides a CML clock frequency dividing circuit. The CML clock frequency dividing circuit comprises a buffer stage circuit and a frequency dividing stage circuit which are electrically connected. Wherein the buffer stage circuit is used for receiving an input clock signal, and the clock signal output by the buffer stage circuit is accessed to the control end of the clock signal input by the frequency division stage circuit. Wherein the input and the output of the buffer stage circuit are analog clock signals; the input of the frequency division level circuit is an analog clock signal, and the output of the frequency division level circuit is a digital clock signal. According to the CML clock frequency dividing circuit, a two-stage circuit structure is adopted, only one set of fixed bias current Ibias needs to be arranged, and compared with the mode that two sets of fixed bias current Ibias are arranged in the prior art, the overall power consumption is obviously reduced.

Description

technical field [0001] The invention relates to a CML clock frequency division circuit, a secondary clock frequency division circuit and an analog-to-digital converter. Background technique [0002] The analog-to-digital converter (Analog-to-Digital Converter, ADC) is an important device that converts analog signals into digital signals, and its sampling rate determines the conversion rate from analog signals to digital signals. [0003] The high-speed ADC has relatively high requirements on the input clock signal, and the quality of the directly input high-frequency clock signal is often difficult to meet the requirements. Therefore, it is usually to input a low-frequency clock signal, and then multiply the frequency of the clock signal inside the chip to achieve the high-speed ADC design. Clock frequency. Further, because the clock signal frequency of the high-speed ADC is too high, the chip often uses multi-channel combined with time interleaving technology for signal co...

AI Technical Summary

Problems solved by technology

[0007] The purpose of the present invention is to provide a novel CML clock frequency division circuit with lower power consumption for the problem of high power consumption of the CML clock frequency division circuit in the prior art

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