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EDA circuit failure analysis method based on deep metric learning

A technology of metric learning and circuit failure, applied in neural learning methods, electrical digital data processing, biological neural network models, etc., can solve the problems of low simulation efficiency and accuracy, and achieve the effect of excellent simulation speed

Pending Publication Date: 2022-03-04
SUZHOU KUANWEN ELECTRONICS SCI & TECH
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Problems solved by technology

However, once the paranoid function is unreasonably selected, the simulation efficiency and accuracy of the importance sampling method will be even lower than that of the traditional Monte Carlo simulation method.

Method used

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  • EDA circuit failure analysis method based on deep metric learning
  • EDA circuit failure analysis method based on deep metric learning
  • EDA circuit failure analysis method based on deep metric learning

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Embodiment Construction

[0028] Such as Figure 1 ~ Figure 4 Shown, the EDA circuit failure analysis method based on deep metric learning of the present invention comprises the following steps:

[0029] Step 1. Perform Monte Carlo sampling on the EDA circuit samples according to the original distribution, generate Monte Carlo sampling samples, and perform Monte Carlo simulation to obtain failure simulation results;

[0030] In specific implementation, the Monte Carlo (MC) method generates a large number of samples through random sampling, according to the formula unit failure rate p cell for Among them, I cell It is an indicator function for judging whether a circuit fails or not, and X is an N-dimensional random vector [x 1 , x 2 , x 3 ......x N ] T , x i (i=1, 2,..., N) is a sampling sample that satisfies the process deviation distribution, f(x) is a function to measure circuit performance, f 0 is the critical value, N is the total number of samples, and the value of i is a natural numbe...

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Abstract

The invention discloses an EDA (Electronic Design Automation) circuit failure analysis method based on depth metric learning, which comprises the following steps of: 1, carrying out Monte Carlo sampling on an EDA circuit sample according to original distribution to generate a Monte Carlo sampling sample, and carrying out Monte Carlo simulation to obtain a failure simulation result; 2, training a depth metric learning model capable of distinguishing failure samples through the Monte Carlo sampling samples and failure simulation results in the step 1; 3, generating enough failure analysis samples for the EDA circuit to be subjected to failure analysis by adopting a Monte Carlo sampling method, and screening the samples by utilizing the depth measurement learning model trained in the step 2 to screen out possible failure samples; and 4, SPICE circuit simulation is carried out on the possible failure sample, a failure EDA circuit is obtained, and the failure rate is calculated. The method is high in simulation efficiency and high in reliability, and has obvious advantages in simulation analysis of large-scale circuits in advanced processes.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design simulation, and in particular relates to an EDA circuit failure analysis method based on deep metric learning. Background technique [0002] With the development of the integrated circuit industry, SRAM has become an indispensable part of electronic products, and the research on SRAM has always been one of the hot spots. In the low-voltage scenario of advanced technology, due to the influence of process parameter fluctuations, the SRAM design margin is significantly reduced, and the tolerable failure probability is getting lower and lower. For this kind of extremely small failure probability problem, the traditional yield analysis method based on the Monte Carlo method requires too much simulation calculation, and the method based on important sampling, such as HDIS (High Dimensional Importance Sampling) and HSCS (Hyper Spherical Clustering nd Sampling) The algorithm is highly d...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/367G06K9/62G06N3/04G06N3/08
CPCG06F30/367G06N3/08G06N3/045G06F18/24133
Inventor 张立军严雨灵马利军张重达娄圆
Owner SUZHOU KUANWEN ELECTRONICS SCI & TECH
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