Device for FPGA, program dynamic loading method and data transmission method

Abstract

The invention relates to the technical field of embedded system application, and discloses a device for an FPGA, the device comprises an upper computer; a Zynq chip which is configured to establish a first program loading channel based on a PCIe bus protocol between the Zynq chip and the upper computer; the FPGA chip which is configured to establish a second program loading channel based on the PCIe bus protocol between the FPGA chip and the Zynq chip; the upper computer sends a to-be-loaded program file to the Zynq chip through the first program loading channel, and the Zynq chip sends the to-be-loaded program file to the FPGA chip through the second program loading channel, so that the FPGA chip loads the to-be-loaded program file. According to the device, the loading rate of the FPGA chip to the program file and the data transmission continuity can be improved, and the integration and the integration degree of the platform are improved. The invention further discloses a FPGA program dynamic loading and data transmission method.

Description

technical field [0001] The present application relates to the technical field of embedded system application, for example, relates to a device for FPGA, a method for dynamically loading programs and a method for data transmission. Background technique [0002] Field Programmable Gate Array (Field Programmable Gate Array, FPGA) is a field programmable logic device based on Static Random-Access Memory (SRAM), and is a core device in a software radio platform. With the increasing demand for flexibility and openness of modern communication systems, software radio platforms have new requirements for loading program files on FPGA chips. [0003] In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in related technologies: [0004] When the existing software radio platform loads the program file of the FPGA chip, it needs to re-power on or reload the entire system. While affecting the work of other devices...

AI Technical Summary

Problems solved by technology

[0004] When the existing software radio platform loads the program file of the FPGA chip, it needs to re-power on or reload the entire system. While affecting the work of other devices, the loading process is also cumbersome and complicated.

At the same time, when the working mode of the Joint Test Action Group (JTAG) is adopted, it is not a common link mode of the software radio platform, and external lines are required, which leads to a poor degree of integration and integration, and there is no Realize dynamic loading in the true sense

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