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Test method, test system, equipment and readable storage medium

A test method and technology of test instructions, applied in fault hardware test method, computer-aided design, error detection/correction, etc., can solve the problem of long simulation test time, and achieve the effect of improving simulation test efficiency and shortening simulation test time.

Pending Publication Date: 2021-12-17
HYGON INFORMATION TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, as the scale and complexity of integrated circuits continue to increase, the time for simulation testing is getting longer and longer

Method used

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  • Test method, test system, equipment and readable storage medium
  • Test method, test system, equipment and readable storage medium
  • Test method, test system, equipment and readable storage medium

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Embodiment Construction

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0025] figure 1 Schematic illustration of the verification process for an integrated circuit design. After using a hardware description language, such as SystemVerilog language, to realize integrated circuit design (hereinafter referred to as design), it is necessary to use SystemVerilog language to build a verification platform, and write test cases (test case), and conduct simulation tests on the design to verify whether the function of the design is Consis...

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Abstract

The invention provides a test method, a test system, equipment and a readable storage medium, and the method comprises the steps: generating a first test instruction which is used for controlling the execution of a first test on a designed test case; obtaining a test log generated in the execution process of the first test and analyzing the test log; determining whether a second test instruction is generated or not according to the analysis result, wherein the second test instruction is used for controlling execution of a second test on the designed test case, and the test result of the second test is different from the test result of the first test. That is to say, the test log does not need to be analyzed manually, whether the second test instruction is generated or not is determined according to the analysis result, the test log is analyzed automatically, and whether the second test instruction is generated or not is determined automatically according to the analysis result of the test log. Whether the second test is executed or not is automatically determined according to the analysis result of the test log, so that the simulation test time can be shortened, and the simulation test efficiency can be improved.

Description

technical field [0001] The embodiments of the present invention relate to the technical field of integrated circuit design, and in particular to a testing method, testing system, equipment and a readable storage medium. Background technique [0002] In integrated circuit design, it is necessary to use a hardware description language (that is, a hardware programming language) to describe the hardware circuit into a register transfer level logic code, use a simulation tool to simulate the logic code, and then use a synthesis tool to convert the logic code into a gate-level circuit netlist, and then use automatic place and route tools to convert the netlist into the circuit routing structure to be implemented. [0003] However, as the scale and complexity of integrated circuits continue to increase, the time for simulation testing is getting longer and longer. Based on this, how to improve the simulation test efficiency and shorten the simulation test time has become one of th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22G06F30/398
CPCG06F11/2273G06F11/2215G06F30/398
Inventor 车胜
Owner HYGON INFORMATION TECH CO LTD
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