Image feature data extraction method, system and related device

Abstract

The invention provides an image feature data extraction method, which comprises the following steps: acquiring image feature data, and determining a corresponding parallel channel number; taking the number of parallel channels as the depth of the image feature data, and increasing the height of the image feature data; using a preset number of RAMs of the FPGA as first-level caches of the DDR for data multiplexing; and configuring a register corresponding to the convolution kernel at the rear end of the first-stage cache, and outputting the image feature data line by line by utilizing the register. According to the invention, the read-write efficiency of the DDR can be improved to the maximum extent, uninterrupted data output of the assembly line is realized, meanwhile, the data reading pressure of the DDR is reduced, and the input requirement of a rear-end high-bandwidth convolution calculation unit can be met. The invention also provides an image feature data extraction system, a computer readable storage medium and electronic equipment, which have the above beneficial effects.

Description

technical field [0001] The present application relates to the field of data processing, in particular to a method, system and related devices for extracting image feature data. Background technique [0002] Currently, CNN (Convolutional Neural Networks, Convolutional Neural Networks) convolutional data extraction process mainly has the following two implementation methods: [0003] 1. Cache the image feature data into the off-chip DDR (Dynamic Random Access Memory, Dynamic Random Access Memory) of FPGA (Field-Programmable Gate Array, and read only 3*3 data each time for volume By using multiple reads of small-scale DDR, the pressure on FPGA storage resources is reduced, the difficulty of wiring is reduced, and the rate of convolution multiplication of the back-end pipeline is improved. [0004] Because 3*3 data is equivalent to three 3*1 data, to read a 3*3 data, you need to send 3 read and refresh commands to the DDR, and the address needs to jump, and the small data read ...

AI Technical Summary

Problems solved by technology

Even though the current partial optimization algorithm can realize the pipeline convolution calculation of 3*11 data, but each time the 11*3 data is read, it still cannot fully release the reading and writing ability of DDR, which becomes the bottleneck of the system computing speed

[0005] 2. Read all the data into the FPGA, you can read 3*3 data at any position within one cycle, and use it for back-end convolution calculations, but the disadvantage of FPGA is that the internal RAM resources are very expensive and small, and generally The size of 5MB is rarely reached. The data of one input channel is generally less than 512*512*8bit, and the data of 20 input channels can only be stored at most. Assuming that the data of 16 channels is ping-pong cached, the RAM resources in the FPGA will be too much. The RAM of the FPGA is evenly distributed, resulting in the need for large-area serial wiring, resulting in wiring congestion, design implementation is extremely difficult, low efficiency, and the more input channels, the more inappropriate this method is, and it is not suitable for expansion

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