Low-delay non-maximum suppression method and device based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a low-delay non-maximum suppression method and device based on an FPGA (Field Programmable Gate Array), which omit an overall sequencing step required by each existing NMS (Network Management System) algorithm, reduce starting delay and meet different calculation speed and precision requirements through flexible parameter configuration. A pipeline architecture is adopted, the method can be compatible with a neural network accelerator of the pipeline architecture, and the overall delay of a target detection algorithm is shortened.

Description

technical field [0001] The invention belongs to the technical field of target detection, and relates to an FPGA-based low-delay non-maximum suppression method and device. Background technique [0002] The target detection algorithm based on neural network has become the mainstream target detection algorithm due to its high precision, and the field-programmable gate array (Field-Programmable Gate Array, FPGA) platform has become a commonly used algorithm deployment platform due to its advantages of high flexibility and low cost. [0003] However, research on low-latency hardware implementation of target detection algorithms usually focuses on accelerating the neural network part, while ignoring the optimization of the post-processing part. Among them, the non-maximum suppression (Non-Maximum Suppression, NMS) algorithm is a common post-processing algorithm, the traditional NMS algorithm steps see figure 1 . Because the traditional NMS algorithm requires multiple overall sor...

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Problems solved by technology

[0008] Aiming at the problem of long time delay in the above-mentioned existing NMS algorithm and device, the present invention proposes a low-delay non-maximum value suppression method and device based on FPGA

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