On-chip bidirectional electrostatic protection apparatus for medium-voltage integrated circuit

A technology for integrated circuits and electrostatic protection, applied in circuits, electrical components, electrical solid devices, etc., to achieve high maintenance voltage and consistent electrical characteristics

Pending Publication Date: 2021-11-09
武汉喻家山微系统有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] In order to solve the above-mentioned problems in the prior art, the present invention provides a bidirectional symmetrical SCR device (DDGCSCR) with low trigger and latch-up immunity characteristics. Its electrostatic protection capability per unit area is very high, which can make the entire circuit design area It is optimized; its bidirectional symmetrical structure can meet the bidirectional electrostatic protection requirements between two ports, further optimizing the product design area and development cost; the device has a very high sustain voltage, which overcomes the traditional SCR and bidirectional SCR devices The latch-up problem faced, but also avoids the phenomenon that the robustness of the device is greatly reduced due to the increase of the holding voltage

Method used

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  • On-chip bidirectional electrostatic protection apparatus for medium-voltage integrated circuit
  • On-chip bidirectional electrostatic protection apparatus for medium-voltage integrated circuit
  • On-chip bidirectional electrostatic protection apparatus for medium-voltage integrated circuit

Examples

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Comparison scheme
Effect test

Embodiment 1

[0047] See figure 1 , figure 1 Is a device cross-sectional view of an embodiment of the present invention to provide a device having a bidirectional symmetric low trigger SCR latch and immunizing properties (DDGCSCR), comprising:

[0048] P-type substrate 1a, is provided on the P-type substrate 1a deep N-well 2a, 2a of the deep N-well is left to right on the first P-well 3a, N-well 4a, a second P-well 5a, wherein the first P-well 3a and the second P-well and N-well 4a 5a respectively adjacent to, the first and second P-well and P-well 3a 4a 5a symmetrically about the N-well and consistent.

[0049] The first P-wells 3a sequentially from left to right with the first P + implanted region 31a, the first N + implanted region 32a and the second N + implanted regions 33a, implantation of the first P + region 31a and the first N + implanted region 32a is provided between the field oxide structure 6a, the first N + implanted region 32a and the second surface between the N + implanted regi...

Embodiment 2

[0073] In order to further illustrate the beneficial effects of the present invention, the DDGCSCR device according to the present invention produces the DDGCSCR device in a CMOS process environment of 0.18 microns, and analyzes the device for current-voltage characteristics by a transmission line pulse (TLP) test. Verified by the DDGCSCR device provided by the above embodiment.

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Abstract

The invention provides an on-chip bidirectional electrostatic protection apparatus for a medium-voltage integrated circuit. The apparatus comprises more than one DDGCSCR device, the DDGCSCR represents a bidirectional symmetric SCR, each DDGCSCR device is in bilateral symmetry in structure, and when currents of the same magnitude flow into the DDGCSCR devices from an anodes and a cathode, the electrical characteristics are consistent. Each DDGCSCR device comprises a P-type substrate, a deep N well, a first P well, an N well and a second P well, wherein the deep N well is arranged on the P-type substrate, the first P well and the second P well are respectively adjacent to the N well, and a first P+ injection region, a first N+ injection region and a second N+ injection region are sequentially arranged in the first P well from left to right; a first gate oxide structure is arranged on the surface between the first N+ injection region and the second N+ injection region; and a first bridge-shaped P+ injection region is arranged between the N well and the first P well, and the second P well and the first P well are symmetrically arranged.

Description

Technical field [0001] The present invention relates to the field of electrostatic discharge protection semiconductor integrated circuit chip technology, and more particularly, high robustness, latch immunized bidirectionally conductive static protection (ESD) device structure having a relatively low trigger voltage. Background technique [0002] As the semiconductor industry technology continues to improve, the industry for product reliability evaluation of more stringent ESD protection integrated circuit reliability testing has become an important part of the evaluation process. Therefore, the reliability of the on-chip ESD protection unit, practicality, and the manufacturing cost of the entire IC industry will have far-reaching effects. To achieve full-chip ESD protection integrated circuit chip to be protected, all input / output (I / O), power and ground are required between a design may provide electrostatic current discharge path. [0003] Industry is currently widely used...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02
CPCH01L27/0248H01L27/0262H01L27/0296
Inventor 钱江陈瑞博
Owner 武汉喻家山微系统有限公司
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