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Layout method and device of mask and mask

A layout method and mask technology are applied in the field of mask, mask layout method and device, which can solve the problems of low efficiency and poor accuracy of manual layout marking patterns, improve space utilization, and solve time-consuming problems. Long, improve the effect of placement accuracy

Pending Publication Date: 2021-10-22
CHANGXIN MEMORY TECH INC
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

[0004] Embodiments of the present invention provide a mask layout method and device, and a mask to solve the problem of low efficiency and poor accuracy of manual layout marking graphics

Method used

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  • Layout method and device of mask and mask
  • Layout method and device of mask and mask
  • Layout method and device of mask and mask

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Embodiment Construction

[0025] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, the drawings only show some but not all structures related to the present invention.

[0026] figure 1 This is a schematic flowchart of a mask layout method provided by an embodiment of the present invention. An embodiment of the present invention provides a mask layout method, which is used to realize various patterns of the mask by the layout device. Automatic layout of split first marker graphics, such as figure 1 As shown, the mask layout method of this embodiment includes the following steps:

[0027] S110 , forming chip patterns arranged in an array on the mask; a dicing line is formed between every two adja...

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Abstract

The invention discloses a layout method and device of a mask and a mask. The layout method of the mask comprises the following steps that: chip patterns arranged in an array are formed on the mask; a cutting channel is formed between every two adjacent chip patterns, and the cutting channels are used for setting mark patterns, wherein the mark patterns at least comprise a first mark pattern; a set number of segmentation units of the first mark pattern is acquired according to a measurement alignment requirement of the first mark pattern; the set number of segmentation units are sequentially arranged on the cutting channels, so that the first mark pattern does not cover other mark patterns; and first mark pattern single bodies are set to replace at least two adjacent segmentation units, and the first mark pattern single bodies are arranged on the cutting channels, the first mark pattern single bodies are completely overlapped with a pattern formed by splicing at least two adjacent segmentation units. According to the layout method and device of the mask and the mask provided by the technical schemes provided by the invention, the problems of low efficiency and low accuracy of manual layout and marking of the graph can be solved.

Description

technical field [0001] The present invention relates to the technical field of semiconductor layout, and in particular, to a mask layout method and device, and a mask. Background technique [0002] In the process of semiconductor manufacturing, the photolithography process is the most important circuit pattern transfer process, wherein, a mask is an important material for realizing the photolithography process, which can be used to manufacture the circuit layout of the semiconductor chip. In the semiconductor processing mode, the IC design company first designs the wafer circuit diagram, and the mask company designs the mask frame data, and combines the wafer circuit diagram and the mask frame data to form a mask. [0003] The reticle frame data generally includes mark patterns (marks) of process and electrical parameters related to various fabrication processes. According to the required marking pattern and chip size, the size of various marking patterns can be calculated,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F1/42G03F1/70
CPCG03F1/42G03F1/70G03F7/70433H01L23/544H01L2223/54426H01L2223/5446
Inventor 李静
Owner CHANGXIN MEMORY TECH INC
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