TSV multi-stress reliability test chip structure and device based on lead bonding

Abstract

The invention relates to a TSV multi-stress reliability test chip structure and device based on lead bonding. The chip structure comprises a silicon substrate, a top electrode, and abottom electrode, wherein a plurality of TSV structures penetrating through the upper surface and the lower surface of the silicon substrate are arranged on the silicon substrate in an array manner; the top electrode is located on the upper surface of the silicon substrate and used for being connected with the top of the TSV structure; the bottom electrode is located on the lower surface of the silicon substrate and used for being connected with the bottom of the TSV structure; and the top electrode and the bottom electrode on the silicon substrate are selectively connected with the end parts of the TSV structures respectively to form a daisy chain interconnection structure or a Kelvin chain interconnection structure. The test device comprises a fixed supporting plate, a test circuit board, a multi-stress loading device, a signal acquisition device and the like. According to the scheme, multi-stress loading can be conveniently and comprehensively carried out on an actual single TSV or multiple TSV link structures, and the reliability of the TSV structure can be scientifically, comprehensively and accurately evaluated through a test means.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a TSV multi-stress reliability test chip structure and device based on wire bonding. Background technique [0002] As the advanced chip manufacturing process moves towards 3nm, the density of transistors on the two-dimensional plane of the wafer is gradually approaching the physical limit, accompanied by a substantial increase in chip development costs and an extension of the development cycle. Thus, "Moore's Law" has failed. Therefore, a three-dimensional integrated package based on a through silicon via (Through silicon vias, TSV) structure emerges as the times require. Three-dimensional integrated packaging integrates wafers in the vertical direction through TSV and stacking, so as to obtain packaged chips with smaller size, higher bandwidth, lower latency, and higher performance, and can also be integrated with microelectromechanical systems (MEMS) Realize heterogeneous integr...

AI Technical Summary

Problems solved by technology

However, the current research on the reliability of TSV structures is basically based on finite element thermal simulation, and there is a lack of experimental research.

The few experimental studies have designed dedicated TSV test chips, and carried out thermal cycle and electrical bias tests on them, but these chips and test circuits cannot achieve multi-stress loading

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