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ESD protection transistor and ESD protection method of CMOS device

A technology of transistors and devices, applied in the field of electrostatic protection, can solve problems such as degradation, CMOS device damage, and failure performance

Pending Publication Date: 2021-09-14
SHENZHEN HORB TECH CORP LTD
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

[0004] The object of the present invention is to provide an ESD protection method for an ESD protection transistor and a CMOS device, to solve the problem that the CMOS device is affected by ESD in the prior art, causing damage, failure or performance reduction of the CMOS device

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  • ESD protection transistor and ESD protection method of CMOS device
  • ESD protection transistor and ESD protection method of CMOS device
  • ESD protection transistor and ESD protection method of CMOS device

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Embodiment Construction

[0021] The ESD protection method for the ESD protection transistor and the CMOS device proposed by the present invention will be further described in detail below with reference to the drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0022] In addition, each embodiment of the content described below has one or more technical features respectively, but this does not mean that the inventor must implement all the technical features in any embodiment at the same time, or can only implement different embodiments separately. Some or all of the technical features. In other words, on the premise that the implementation is possible, those skilled in the art can selectively im...

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Abstract

The invention provides an ESD protection transistor and an ESD protection method of a CMOS device. The ESD protection transistor comprises a substrate, a buried dielectric layer and a surface semiconductor layer, wherein the buried dielectric layer is formed on the substrate, and the surface semiconductor layer is formed on the buried dielectric layer; an open data link interface transistor is formed in the surface semiconductor layer. On the basis of the structural design of the ESD protection transistor, the protection capability of the transistor is improved, so that effective ESD protection is carried out on the CMOS device, and the problems of damage, failure or performance reduction of the CMOS device caused by ESD are avoided.

Description

technical field [0001] The invention relates to the technical field of electrostatic protection, in particular to an ESD protection transistor and an ESD protection method for a CMOS device. Background technique [0002] Electro-static discharge (ESD) is a discharge process of static electricity accumulated in insulating materials, but this process will cause damage, failure or performance degradation to a large number of transistors, diodes and other microstructures in integrated circuits. In particular, various CMOS devices are extremely sensitive to ESD, and electrostatic voltages of tens of volts, even tens of volts, or even a few volts can cause melting, soft breakdown, and hard breakdown of various microstructures. Therefore, ESD protection is a major issue facing the entire IC. [0003] With the continuous improvement of IC integration, the requirements for ESD protection technology are becoming more and more stringent. For how to effectively protect CMOS devices fro...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L27/02
CPCH01L29/7841H01L27/0266
Inventor 顾大元乔畅君韩玲玲孙可平
Owner SHENZHEN HORB TECH CORP LTD
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