QC-LDPC encoding method and encoder

An encoding method and encoder technology, applied in the field of QC-LDPC encoding method and encoder, can solve the problems of large amount of calculation and high complexity of hardware implementation

Pending Publication Date: 2021-08-20
南京宁麒智能计算芯片研究院有限公司
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  • Abstract
  • Description
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Problems solved by technology

[0008] Aiming at the problems of traditional QC-LDPC encoding in the prior art with a large amount of computation and high hardware implementation complexity, the present invention provides a QC-LDPC encoding method and encoder, which saves storage resources, simplifies the operation process, and can be realized by Highly parallel encoding operation, finally can support LDPC encoding operation with 1 / 2 code rate and 19 code lengths under IEEE 802.16e communication protocol

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  • QC-LDPC encoding method and encoder
  • QC-LDPC encoding method and encoder
  • QC-LDPC encoding method and encoder

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Embodiment

[0047] The encoder described in this embodiment takes the 1 / 2 code rate LDPC encoding under the IEEE 802.16e standard as an example to describe the encoder and the encoding method. In practical applications, different parallel calculation paths can be adapted according to different standards. Support different QC-LDPC encoding standards.

[0048] In the scheme described in this embodiment, the base parity check matrix H b The number of rows and columns is m b and n b express. For different code rates, n b Both are 24, m at 1 / 2 code rate b =12. Before expanding the base check matrix, an expansion parameter z is selected, and H b expands to m b · z×n b Check matrix H of z; record m=m b z,n=n b z, the size of the check matrix H is recorded as m×n; according to the IEEE802.16e standard, the extended parameter z can be one of a series of 19 values ​​in total, of which the minimum is 24 and the maximum is 96, with an interval of 4 values, the 19 code lengths supported by ...

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Abstract

The invention discloses a QC-LDPC encoding method and an encoder, and belongs to the technical field of QC-LDPC encoding. Only the generator of the cyclic matrix is stored, storage resources are saved, the coding storage amount and the transportation amount are simplified, the hardware implementation complexity is reduced, and therefore the power consumption of the encoder is reduced; a cyclic shift unit and a binary field multiply-add unit are adopted, and an AND operation and an XOR operation are used to realize coding operation of a generated matrix and an information bit, so that the operation process is simplified; through a high-parallelism-degree storage mode, generator elements of a generator matrix are pre-read and then sent to a shift register for calculation at the same time, so that high-parallelism-degree coding operation can be realized; efficient LDPC encoding operation of 1 / 2 code rate and 19 code lengths under an IEEE 802.16 e communication protocol can be supported; the method has the advantages of being low in hardware complexity and high in storage resource utilization rate, and finally high-parallelism and high-throughput coding operation can be achieved.

Description

technical field [0001] The present invention relates to the technical field of QC-LDPC encoding, and more specifically, relates to a QC-LDPC encoding method and an encoder. Background technique [0002] Low-density parity-check code (LDPC code) is a sparse check matrix linear block code, which was first proposed by Robert Gallager in the 1960s. Its performance is close to the Shannon limit, and it is a widely used communication and navigation algorithm. Therefore, designing an LDPC encoding method with high parallelism, low calculation load and easy hardware implementation and hardware implementation is a research hotspot today. [0003] If the length of the LDPC code check bit is m, the length of the code word after encoding is n, and the check matrix is ​​H m×n It means that the length k=n-m of the information sequence s, then the code rate r=k / n. The corresponding generator matrix G is obtained by transforming the parity check matrix, and then the information sequence s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
CPCH03M13/116
Inventor 李丽徐瑾杨和平赵仁港傅玉祥何书专陈健
Owner 南京宁麒智能计算芯片研究院有限公司
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